SN65DPHY440SS: Max distance between DPHY retimer( SN65DPHY440SS) and CSI-2 Sink when MIPI lane speed 360Mbps

HI,

I don't see an issue with 6in trace running at 360Mbps data rate. The DPHY440 has RX equalizer that can help compensating the 6in insertion loss. Depending on the insertion loss, EQ set to VIM should be sufficient.

I would recommend having the pullup/pulldown option on the configuration pins so we can tune the DPHY440 as needed.

Thanks

David

Hi David,

Looks misunderstanding on 6 inches.

6 inch distance is between DPHY retimer and processor ( CSI-2 sink). I can not place DPHY retimer less than 6 inch on the existing board  

Hi,

The DPHY440 TX has a pre-emphasis of 2.5dB that can be used to compensate for the insertion loss on the TX side, so I don't see 6in at 360Mbps being an issue here. If the processor module RX has equalizer, then additional loss can be compensated by the RX equalization

Thanks

David 

Hi David, Thanks for quick response

Processor receive module  doesn't have receive equalization. Please confirm DPHY Re-timer drive 6inch FR4 trace with 2.5dB pre-emphasis setting.

Please confirm what resistors to be populated? R1 and R2=10K?? R7 should be populated or R8 should be populated.

Hi,

Just want to clarify, is the 360Mbps the total data rate or the line rate (data rate per lane)? How many MIPI lanes do you plan to use and what is your minimum high speed clock frequency?

6in insertion loss depends on the trace width, the board  dielectric constant, etc. For example, if you have 5mil wide trace, the loss is ~0.15dB/in. 6in loss will be 0.9dB. This is the estimated loss of the trace only without adding the loss from the via, the connector, etc.

For configuring the DPHY440, please refer to section 8.2.2 Detailed Design Procedure.

Thanks

David

Hi David,

Camera sesnsor interface is using 1 MIPI CLK lane+ 1 Data lane only. Below speeds in snippet are supported by the camera sensor.

Please confirm.

Hi David,

I have started testing of DPHY440 Re-timer in the design. I am getting the start of transmission multi bit error on data lane. 

Below is the processor register bit description.

“CILA_DATA_LANE0_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi
bit start of transmission byte error in one of the packets SOT bytes on data lane-0. The packet will be
discarded.”  

 DPHY440 configured as below:

• VSADJ_CFG0: Pulled-up with 10K
• PRE_CFG1: Pulled-up with 10K
• EQ/SCL: Pulled down

Please suggest to solve the issue.

HI,

Can I take a look at your schematic and layout? How long is the trace before the DPHY440 and after the DPHY440?

Are you only seeing the errors on lane 0 and do you have a scope that can be used to probe the failing lane?

Thanks

David