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TCAN4550: CAN Frame Error

Part Number: TCAN4550

Hi,

We are trying to send and receive CAN frame continuously but we observed the frames  which is getting received is not the updated one ,as we see older frames . We suspect that MCAN data memory is holding the older frame and we are unable to find  API  which  clears the MCAN data memory. We have used the sample code provide by you. Kindly guide us to find the API or the action needed to be taken to clear the MCAN older frame/data.

Below mentioned the sequence of action we are performing.

1. Transmit dummy Payload.

2. Receive payload.

3. Transmit the Received Payload.

Below is the code snippet we followed to receive and transmit in loop.

uint8
Receive_CANFD(uint8_t *dataPayload)
{
uint32_t readdata;
uint8_t numBytes = 0;
TCAN4x5x_Device_Interrupts dev_ir ; // Define a new Device IR object for device (non-CAN) interrupt checking
TCAN4x5x_MCAN_Interrupts mcan_ir ; // Setup a new MCAN IR object for easy interrupt checking

do{
TCAN4x5x_Device_ReadInterrupts(&dev_ir); // Read the device interrupt register

}while(dev_ir.M_CAN_INT != 1);
TCAN4x5x_Device_ClearInterrupts(&dev_ir);

do{
mcan_ir.RF0N = 0;
TCAN4x5x_MCAN_ReadInterrupts(&mcan_ir); // Read the interrupt register
}while(mcan_ir.RF0N != 1 ); //Wait for Receive Frame

if (mcan_ir.RF0N == 1 ) // If a new message in RX FIFO 0
{
TCAN4x5x_MCAN_RX_Header MsgHeader = {0}; // Initialize to 0 or you'll get garbage
numBytes = TCAN4x5x_MCAN_ReadNextFIFO( RXFIFO0, &MsgHeader, dataPayload); // This will read the next element in the RX FIFO 0
TCAN4x5x_MCAN_ClearInterruptsAll();
}
return numBytes;

}

/*Transmit API*/

void
Transmit_CANFD(TCAN4x5x_MCAN_TX_Header *header, uint8_t *dataPayload)
{

TCAN4x5x_MCAN_WriteTXBuffer(0, header, dataPayload);
TCAN4x5x_MCAN_TransmitBufferContents(0);

}

Attached snapshot for Reference.

In the above snapshot first byte of data we are updating and fourth byte  is the no of frames.

Regards,

Kumar Ashutosh

  • Kumar,

    Thanks for bringing this to our attention. Do you have these memory blocks configured as FIFO? And what is are the contents of registers 0x10A4 and 0x10B0?

    Regards,

  • Hi Eric,

    Thankyou for your response.

    Yes we have configured the memory blocks as FIFO. I have read the Registers as mentioned above and below is my observation.

    Before Transmit  both register value is zero and after we receive first frame register 0x10A4  value is 0x00010001 and 0x10B0 is zero. Value of Register  0x10A4 keeps on incrementing after every receive and Register 0x10B0 is always reading Zero.

    Register 0x10A4 value after second Receive = 0x00020002

    Register 0x10A4 value after Third Receive    = 0x00030003 and so on.

    Please let me know if you need further information.

    Regards,

    Kumar Ashutosh

  • Hi Eric,

         Can you please update on the above mentioned issue.

         Please let me know if you need further information.

    Regards,

    kumar Ashutosh

  • Hi Eric,

      Can you highlight the difference between two configuration shown below.

    CONF:- 1

    TCAN4x5x_MRAM_Config MRAMConfiguration = {0};

    MRAMConfiguration.SIDNumElements = 1; // Standard ID number of elements, you MUST have a filter written to MRAM for each element defined
    MRAMConfiguration.XIDNumElements = 1; // Extended ID number of elements, you MUST have a filter written to MRAM for each element defined
    MRAMConfiguration.Rx0NumElements = 5; // RX0 Number of elements
    MRAMConfiguration.Rx0ElementSize = MRAM_64_Byte_Data; // RX0 data payload size
    MRAMConfiguration.Rx1NumElements = 0; // RX1 number of elements
    MRAMConfiguration.Rx1ElementSize = MRAM_64_Byte_Data; // RX1 data payload size
    MRAMConfiguration.RxBufNumElements = 0; // RX buffer number of elements
    MRAMConfiguration.RxBufElementSize = MRAM_64_Byte_Data; // RX buffer data payload size
    MRAMConfiguration.TxEventFIFONumElements = 0; // TX Event FIFO number of elements
    MRAMConfiguration.TxBufferNumElements = 2; // TX buffer number of elements
    MRAMConfiguration.TxBufferElementSize = MRAM_64_Byte_Data; // TX buffer data payload size

    CONF:- 2

    TCAN4x5x_MRAM_Config MRAMConfiguration = {0};
    MRAMConfiguration.SIDNumElements = 1; // Standard ID number of elements, you MUST have a filter written to MRAM for each element defined
    MRAMConfiguration.XIDNumElements = 1; // Extended ID number of elements, you MUST have a filter written to MRAM for each element defined
    MRAMConfiguration.Rx0NumElements = 10; // RX0 Number of elements
    MRAMConfiguration.Rx0ElementSize = MRAM_64_Byte_Data; // RX0 data payload size
    MRAMConfiguration.Rx1NumElements = 0; // RX1 number of elements
    MRAMConfiguration.Rx1ElementSize = MRAM_64_Byte_Data; // RX1 data payload size
    MRAMConfiguration.RxBufNumElements = 0; // RX buffer number of elements
    MRAMConfiguration.RxBufElementSize = MRAM_64_Byte_Data; // RX buffer data payload size
    MRAMConfiguration.TxEventFIFONumElements = 0; // TX Event FIFO number of elements
    MRAMConfiguration.TxBufferNumElements = 10; // TX buffer number of elements
    MRAMConfiguration.TxBufferElementSize = MRAM_64_Byte_Data; // TX buffer data payload size

  • Kumar,

    Thanks for your patience, and my mistake in my last reply, I meant to ask for you to read 0x10A0, this will give the RX FIFO 0 configuration. If 0x10B0 is reading back 0, that means that the FIFO size and address haven't been configured as this register is used to configure those settings. And if the size and address are 0, that means there is no FIFO in the memory space.

    The difference between the two configurations is the number of elements in the configured TX Buffer and RX FIFO. The elements are used as the place to store each message received from and transmitted to the CAN bus. Configuration two has more elements in both, thus they can store more messages before having to read the RX FIFO to clear them.

    Regards,

  • Hi Eric,

    Thankyou for your response.

    We have read the register 0x10A0 value we got is 8005000C.

    We have also changed the RxFIFO mode to blocked mode but still we are observing same behaviour.
    Please let us know the future course of action which can solve the issue highlighted in this ticket i.e. receiving older frames.

    Also can you please let us know is there any way we can directly debug the MRAM data.

    Regards,

    Kumar Ashutosh

  • Kumar,

    Just to make sure I understand, you're configuring your RX FIFO 0 for 5 elements but reading out of it every time a new message is received, correct?

    If that's the case then the FIFO element should by empty when a new transmit occurs, and if blocking mode didn't block to reception of a new message in the element, this means that the element was empty at the time of reception. 

    Is it possible to probe CANH and CANL when these errant frames come in so the data being transmitted on the bus can be seen?

    Regards,