• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 305 views
  • Users 0 members are here
Support feedback
Options
Options

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

tms320f28335

Farrukh Abbas
Prodigy 30 points

I am receiving data on transceiver (RS422 driver), and I want to share the RX pin of RS 422 to the micro controller and FPGA as I don't want to add another transceiver (RS422 driver) . Is it works properly or I have to add some passive or active component?

  • 0
    TI__Guru 71526 points

    Hello Farrukh,

    I am not quite clear on what you are wanting to design here.  Do you want to buffer the bus to both the processor and FPGA at the same time?  Or select where the signal is routed, to the processor or FPGA?  A simple diagram would be very helpful.

    Regards,

    ~Leonard 

  • 0 in reply to Farrukh Abbas
    Prodigy 30 points

    As mentioned in above block diagram , I want to receive data on micro controller and also on FPGA that is why sharing the RXD pin of the RS-422 . FPGA don't have the requirement to transmit data.

  • 0 in reply to Farrukh Abbas
    TI__Guru 62920 points

    Hi Farrukh,

    This is typically OK.  To confirm, you could consult the transceiver datasheet for the allowable load current on the RXD output.  This may be its own specification in the Recommended Operating Conditions table or it may be specified indirectly as a test condition to the VOH/VOL specifications in the Electrical Characteristics table.  As long as the load current is less than this value, the device will drive the specified logic output levels.  You could then look at the input current specifications for the FPGA and MCU to make sure their parallel combination does not exceed the maximum loading.

    Regards,
    Max