TL16C2550: TL16C2550 reset behavior

Hey Dai,

""RESET is an active high input." written in the datasheet""

This just means that the pin will go into reset when the signal is HIGH. If this said active low input, then it would mean to enter reset you would need to pull the pin low. This doesn't state the D0-D7 state during a reset condition.

 

"However, D0-D7 state seems to be not Hi-Z during keeping input H to the RESET terminal."

I recently did testing for a customer on a similar device (TL16C550D) and found that the D0-D7 pins did not care about the reset pins state but rather what the read pin (IOR) state was set to.

 

"After change from H to L state to the RESET terminal, D0-D7 seems to be Hi-Z state. (with CSA and B:High state) Is it correct work? (Expected behavior is "D0-D7 are Hi-Z state during H-state to RESET terminal.")"

I would need to get samples and a breakout board for this to verify I got the same results as you but based on my previous testing of the 550D device, I suspect the D0-D7 pins are only be HI-Z if IOR is inactive. It may be possible that the device will also go HI-Z if CSA/CSB are inactive as well.

Would you like me yo place an order for samples and a breakout board to verify I get the same results as you?

-Bobby

Hi Bobby, Thank you for reply. If Read signal is used to any other peripheral device in common, it means the peripheral device cannot control before reset this TL16C2550. In addition, if I use 2 TL16C2550 on same bus, how can I control each device? (with common read signal) Normally, user wants to control some peripheral devices by common signal. Again, expected behavior is the data buses state is Hi-Z during reset state. And I want to know about collect reset sequence. >Would you like me yo place an order for samples and a breakout board to verify I get the same results as you? Please confirm in your environment. Dai

Hi Bobby,

Bobby said:

>Would you like me yo place an order for samples and a breakout board to verify I get the same results as you?

When will you able to check it? Please let me know about the schedule.

Hey Dai,

I'll see if I can place an order for this tonight. I suspect end of the week is when it would arrive. I'll let you know when it does.

-Bobby

Hi, I got it. I wait it. Dai

Hey Dai,

Just an update. I've received the units and breakout boards today and submitted them for soldering. I should have time on Friday to check/test the concern you have. I'll give another update end of day Friday.

-Bobby

Hi Bobby, Thank you for informing. I wait next info. -Dai

Hi Bobby, Any progress?

Hey Dai,

Sorry for the delays, I'll make time tomorrow to get this done.

-Bobby

Hey Dai,

I just finished checking. I drove CSA and IOR low with the address set to 0x05h (the LSR register) and read bits 5 and 7 while the device was held in reset. I was able to see current flow from D5 (driving HIGH) and D7(driving LOW) through an ammeter through some resistors [all while reset was held HIGH] so this confirms the parallel pins (D0-D7) are NOT HI-Z while in reset. HI-Z mode depends if either IOR or CSA/CSB are held HIGH instead....

Thanks and sorry for the delays.

-Bobby

Hi Bobby,

Thank you very much for checking.

HI-Z mode depends if either IOR or CSA/CSB are held HIGH instead.

Is it true?
Could you please check the data buses states(output? Hi-Z?) on the following settings?
*All settings should be applied at the same time.

Pin Settings

- RESET : High(reset state)
- #CSA: High (CSA disabled state)
- #CSB: High (CSB disabled state)
- #IOR : Low(Output Enable)

Expected behavior

All data buses(D[0:7]) state are Hi-Z.
When I use some peripheral ICs around CPU(i.g, ROM, SRAM etc..), usually #OE(#IOR) signal is used as common signal.
So expected behavior is Regardless of #OE(#IOR) state, data buses state are Hi-Z.(with RESET:H/#CSA and #CSB:H)

- Dai

Hey Dai,

I will check this tonight for you.

-Bobby

Hi Bobby,

Thank you.

"Pin Settings

- RESET : High(reset state)
- #CSA: High (CSA disabled state)
- #CSB: High (CSB disabled state)
- #IOR : Low(Output Enable)"

During these conditions, the device's parallel data line is HI-Z. (Matches your expected behavior).

Thanks,

-Bobby

Thank you for quick confirmation.
One more question.
Is the Reset pin kept high ever since power on?
(Is pin has never dropped to a low after power on?)

-Dai

During my tests the other day I did both.

-Bobby

Hi Bobby,
Thank you.
I will check again by myself, and after that I will reply and close (or continue) this topic.

(It takes about a few weeks.)
Dai Aotani