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DP83867ERGZ-S-EVM: Link 1000Mbps without Auto-Neg

Part Number: DP83867ERGZ-S-EVM
Other Parts Discussed in Thread: USB-2-MDIO, DP83867E, DP83867IS, DP83867CS, DP83867CR, DP83867IR

Hello,
I would like to deactivate auto-negotiation using the "RX CTRL" pin of the DP83867ERGZ component.

When I activate auto-negotiation by the "Rx_CTRL" in mode 3, the ethernet link is created with the computer

When I modify the "Rx_CTRL" pin in mode 4 to deactivate auto-negotiation. I cannot find an Ethernet link with a computer configured (see "Config computer" in attachment) :

- Speed : 1000Mbps
- Direction : Full-Duplex
- Auto-negotiation : OFF
However, the "Rx_CLK" pin oscillates at 125Mhz which indicates a 1000-Mbps Mode
Measurement of pin "Rx_CLK" when auto-negotiation is disabled (Mode 4) by pin "Rx_CTRL"  
The state of the registers when the computer is connected with un RJ45 Cable
Register 0000 is: 0140
bit 6 - SPEED SELECTION MSB        Value by default -> 1, RW        Comment -> Speed Select: See description for bit 13.
                                                                                                                                  Speed Select (Bits 6, 13):
                                                                                                                                  When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
                                                                                                                                  10 = 1000 Mbps   
bit 8 - DUPLEX MODE                        Value by default -> Strap, RW  Comment -> Duplex Mode: 
                                                                                                                                   When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected
                                                                                                                                   1 = Full Duplex operation.  
Register 0031 is: 10B0
bit 12 and 4 are reserve
bit 6:5 - SGMII_AUTONEG_TIMER   Value by default -> 01, RW        Comment -> SGMII Auto-Negotiation Timer Duration:
                                                                                                                                   01: 2 µs
bit 7 - INT_TST_MODE_1                 Value by default -> Strap, RW     Comment -> Internal Test Mode 1
                                                                                                                                    This needs to be disabled. The RX_DV/RX_CTRL strap must be configured for strap mode 3 or strap
                                                                                                                                     mode 4. If the RX_CTRL pin cannot be strapped to mode 3 or mode 4, if not this bit must be cleared to 0
                                                                                                                                     through register configuration.
                                                                                                                                    1: Internal Test Mode 1, this bit must be cleared
I cannot create the link between the Phy and a computer
Why does the link to the computer not appear ??  
 
Regards,
Johann
  • Hi Johann,

    Are you in auto-mdix or forced mdi/mdix mode?

    Thanks,

    Cecilia

  • Hello Cecilia,


    The registers concerned by this mode are:

    - PHY Control Register (PHYCR), Address 0x0010

    - PHY Status Register (PHYSTS), Address 0x0011


    State of registers :

    Register 0010 is: 548

    bit 15 - 14 - TX FIFO Depth        Value by default -> 1, RW                 Comment -> TX FIFO Depth:
                                                                                                                                       01 = 4 bytes/nibbles (1000Mbps/Other Speeds)
                                                                                                                                       Note: FIFO is enabled only in the following modes: 1000BaseT + GMII 10BaseT/100BaseTX/1000BaseT + SGMII
    bit 13 - 12 - RX FIFO Depth        Value by default -> 1, RW                 Comment -> RX FIFO Depth:
                                                                                                                                       01 = 4 bytes/nibbles (1000 Mbps/Other Speeds)
                                                                                                                                       Note: FIFO is enabled only in SGMII
    bit 11 - SGMII_EN                       Value by default -> Strap, RW           Comment -> SGMII Enable:
                                                                                                                                       1 = Enable SGMII
    bit 10 - FORCE_LINK_GOOD     Value by default -> 0, RW                 Comment -> Force Link Good:
                                                                                                                                       0 = Normal operation
    bit 9 - 8 - POWER_SAVE_MODE       Value by default -> 0, RW          Comment -> Power-Saving Modes:
                                                                                                                                        00 = Normal mode
    bit 7 - DEEP_POWER_DOWN_EN    Value by default -> 0, RW          Comment -> Deep power-down mode enable
                                                                                                                                        0 = Normal operation.
    bit 6 - 5 - MDI_CROSSOVER   Value by default -> RGZ: 10, RW        Comment -> MDI Crosssover Mode:
                                                                                                                                       1x = Enable automatic crossover
    bit 4 - DISABLE_CLK_125        Value by default -> 0, RW                   Comment -> Disable 125MHz Clock:
                                                                                                                                       0 = Enable CLK125
    bit 3 - RESERVED                    Value by default -> 1, RO                    Comment -> RESERVED: Writes ignored, read as 1.
    bit 2 - STANDBY_MODE          Value by default -> 0, RW                   Comment -> Standby Mode:
                                                                                                                                       0 = Normal operation.
    bit 1 - LINE_DRIVER_INV_EN  Value by default -> 0, RW                   Comment -> Line Driver Inversion Enable
                                                                                                                                       0 = Normal operation.
    bit 0 - DISABLE_JABBER        Value by default -> 0, RW                   Comment -> Disable Jabber
                                                                                                                                      0 = Enable Jabber function.
    Register 0011 is: 0002
    bit 15 - 14 - SPEED SELECTION     Value by default -> 0, RO         Comment -> Speed Select Status:
                                                                                                                                     These two bits indicate the speed of operation as determined by Auto-Negotiation or as set by manual configuration
                                                                                                                                     00 = 10 Mbps
    bit 13 - DUPLEX MODE             Value by default -> 0, RO                Comment -> Duplex Mode Status:
                                                                                                                                     0 = Half Duplex
    bit 12 - PAGE RECEIVED         Value by default -> 0, 0, RO, LH, COR         Comment -> Page Received:
                                                                                                                                                 This bit is latched high and will be cleared upon a read.
                                                                                                                                                  0 = No page received.
    bit 11 - SPEED DUPLEX RESOLVED    Value by default -> 0, RO    Comment -> Speed Duplex Resolution Status:
                                                                                                                                     0 = Auto-Negotiation is enabled and has not completed.
    bit 10 - LINK_STATUS                Value by default -> 0, RO                Comment -> Link Status:
                                                                                                                                     0 = Link is down
    bit 9 - MDI_X_MODE_CD           Value by default -> 0, RO                Comment -> MDI/MDIX Resolution Status for C and D Line Driver Pairs:
                                                                                                                                      0 = Resolved as MDI.
    bit 8 - MDI_X_MODE_AB            Value by default -> 0, RO                Comment -> MDI/MDIX Resolution Status for A and B Line Driver Pairs:
                                                                                                                                      0 = Resolved as MDI.
    bit 7 - SPEED_OPT_STATUS      Value by default -> 0, R0                 Comment -> Speed Optimization Status:
                                                                                                                                       0  = Auto-Negotiation is currently being performed without Speed Optimization.
    bit 6 - SLEEP_MODE                   Value by default -> 0, RO                Comment -> Sleep Mode Status:
                                                                                                                                       0 = Device currently in active mode
    bit 5 - 2 - DISABLE_JABBER        Value by default -> 0, RO                Comment -> Crossed Wire Indication:
                                                                                                                                        Indicates channel polarity in 1000BASE-T linked status. Bits [5:2]
                                                                                                                                        correspond to channels [D,C,B,A], respectively.
    the last register is not consistent with my needs. I think mdi / mdix mode is not set up properly
    Can you help me on this point?
    Johann
  • Hi Johann I will need a couple of days to review these register items. However can you try using different types of cables and seeing if that helps or forcing to the different MDI/X modes?

    Have you also reviewed our DP83867 troubleshooting guide? https://www.ti.com/lit/an/snla246a/snla246a.pdf

    Thanks,

    Cecilia

  • Hi Johann,

    Were you able to test the different cables and review the troubleshooting guide?

    Thanks,

    Cecilia

  • Hello Cecilia,

    My problem is not solved, yet I followed your guide and lowered the link speed to 100Mbps Full duplex without autoneg.

    List of tests performed in the guide :

    Power Supplies et measured the voltage 

       - 1V (1.001V) and capacitors position -> OK

       - 2.5V (2.485V) and capacitors position -> OK

       - V_IO = 2.5V (2.47V) and capacitors position -> OK

    RBIAS Voltage and Resistance -> OK

    Line Driver -> OK

    Verify Key Signals

        - Probe the RESET_N Signal  -> OK

        - Probe the XI Clock -> OK

        - Probe the Strap Pins During Initialization -> OK

        - Probe the Serial Management Interface Signals (MDC, MDIO) -> OK

                   Register 006E is: 0800

                   Register 006F is: 0100

    Probe the MDI Signals -> unrealized because the lien appears between the computer and phy, When the pin "RX_CTRL" is in mode 3. 

    - DP83867 Register Access with USB-2-MDIO software 

    When the pin "RX_CTRL" is in mode 3. the link appears 

    Register 0000 is: 1140 to 2100 
    Register 0001 is: 794D
    Register 0004 is: 01E1
    Register 0005 is: 0000 
    Register 000A is: 0000
    Register 0010 is: 5848
    Register 0011 is: 6C02

    ETH1_MDIB between phy and magnetic, the measurement shows activity on the RJ45

    ETH1_Tx (Tx_D0/1 / SGMII_SIP/N) before Cap coupling, the measurement shows no activity yet the RJ45 is moving

    Why ping is not transmitted by phy ?

    When the pin "RX_CTRL" is in mode 4 and "LED_1" is mode 3, the link does not appear

    Register 006E is: 08A3
    Register 006F is: 0140
    Register 0000 is: 0140 to 2140
    Register 0001 is: 7949
    Register 0004 is: 0181
    Register 0005 is: 0000
    Register 000A is: 0000
    Register 0010 is: 5C48
    Register 0011 is: A802 to E802

    Why does the link not appear in this configuration ?

     

    When the pin "RX_CTRL" is in mode 3 or 4 and "LED_0" is mode 4, the link does not appear

    Because the mirror mode is not necessary

    Built-in Self Test

    // Title: DP83867 PRBS test
    // Location: France
    // Developer: Johann
    // Date: July 23, 2020
    // Force DUT 100Mbps, BIST

    begin

    //delay 100
    001f 8000 // restart core
    0000 2100 // force 100Mbps, full-duplex
    0010 5828 // 5808 - mdi or 5828 - mdix

    // Enable BIST mode
    //echo BIST
    0016 f008 // use termination outside RJ45//Continuous PRBS, Enable checker, Enable PRBS, Transmit 64 packets

    001f 4000
    //delay 200

    // loop 5
    // Reads GEN_STATUS
    // NOTE: First read clears LH, Second read has actual status
    // Value should be 0A40, PBRS checker locked and sync
    0017
    0017
    // NOTE: First read clears LL, Second read has actual status
    0001 //bit 2 will give indication if we have link fails
    0001
    0001
    0001
    0001
    0072 0003 // lock & clear PRBS counters (byte 0x71 and erro 0x72) counters
    0071 // rd byte counter to observe bytes are indeed received
    0072 // rd errors counter. should read 0
    // endloop

    0000

    end

    In all cases this test is active but the results are not conclusive because the registers 0x0071 and 0x0072 report errors 

    Examples :

    Register 0072 is: 0003
    Register 0071 is: AAE7
    Register 0072 is: 0200

    Loopback Modes

    Does the loopback mode work in SGMII ?

    - Establish an MDI Link

       - Link partner transmit problem -> the link partner is the switch VSC7512XMY

       - Cable length and quality -> Ethernet Cable is cat. 5. The link switch side are on the backplane

       - Clock quality of the 25MHz reference clock -> 25MHz_20ppm_18pF

       - MDI signal quality -> see measuerd

    Establish an SGMII Link

    I’m checking the parameters and setting up the manipulation 

    Do you have any suggestions ?

     

    Regards,

    Johann

     

  • We use the 48-pin QFN

  • I’m looking to use loopback mode
    in SGMII


    Do you have a script for the USB-2-MDIO software?

  • I noticed a small difference between my magnectic and the magnetic of Application Report (SNLA246A)

    I’ll make the change

  • I noticed that the DP83867 datasheet has evolved 

    The version on my server date :

    DP83867CS, DP83867IS, DP83867E SNLS504B –OCTOBER 2015–REVISED MARCH 2017

    The version on your date server is younger :

    DP83867IR, DP83867CR SNLS484F –FEBRUARY 2015–REVISED DECEMBER 2019

    What version of datasheet to use in my case?

    Your guide dates :

    Application Report SNLA246A–October 2015–Revised April 2016 DP83867 Troubleshooting Guide

    Do I use the correct version of the guide?

    Johann

  • Hi Johan,

    My apologies I have been out of office.

    I will need to review all your messages that you have sent on July 23rd. I can have my feedback by the end of this week.

    Thank you very much.

    Cecilia

  • Hi Johann,

    In your schematic I see that you are using the RGZ package of the DP83867. With this package when you select between modes for RX_CTRL, you are only able to advertise between 10/100/1000 or 100/1000. 

    You will not be able to force and select only 1000M through strap. You would have to do this advertisement in register configuration. 

    As for the datasheets and app notes, the most up to date documents are currently on the web right now.

    Thanks,

    Cecilia

  • Hello,

    Which registers are presented when the RX_CTRL pin changes from mode 3 to 4 ?

    When I force the link in 100Mbps with my script, the link appears except that I want it in 1Gbps. 


    why the link does not appear in 1Gbps in forced mode?

    Johann

  • Hi Johann,

    RX_CTRL strap is represented by bit 12 of Register 0x0 = Auto-Negotiation Enable

    What speeds are your PC advertising? 

    Thanks,

    Cecilia

  • the PC is configured 1Gbps in full - duplex without auto-neg. 

    I have given you his information since the start of support.

    The value of register 0 is 0x0100 which corresponds to the configuration of the PC

    Johann

  • Hi Johann,

    My apologies it has been some time since we last spoke so I need to recall the issue at hand. 

    As I mentioned in my comments you cannot force the 1G speed. You will have to enable auto-negotiation and through register 0x4 disable the advertisements of 10/100 speeds.

    Thanks,

    Cecilia


  • I don't understand what fourteen I have to modify in register 4


    The current value in register 4 is 01E1

    Johann

  • Hi Johann,

    Please disable bits 8 through 5 as these disable the advertisement to 10/100 speeds on the PHY therefore only advertising 1G in auto-negotiation.

    Right now you are seeing 01E1 which shows that all of bits 8-5 are 1 meaning 10/100 is still advertised.

    Thanks,

    Cecilia


  • The 1G link appears with the trames

    H 4

    Receive Total             Transmit Total
    -------------                   --------------
    Rx Packets:      180   Tx Packets:    2592
    Rx Octets:    25689    Tx Octets:   539960
    Rx Broadcast:    73    Tx Broadcast: 2604
    Rx Multicast:    107    Tx Multicast:     107
    Rx Pause:            0    Tx Pause:             0
    Rx Error Packets 0    Tx Error Packets   0
    Rx MAC Ctrl:       0    Tx -                        -

    Receive Size Counters    Transmit Size Counters
    ---------------------                ----------------------
    Rx 64 Bytes:          20       Tx 64 Bytes: 0
    Rx 65-127 Bytes: 113       Tx 65-127 Bytes: 1498
    Rx 128-255 Bytes: 29       Tx 128-255 Bytes: 752
    Rx 256-511 Bytes: 14       Tx 256-511 Bytes: 107
    Rx 512-1023 Bytes: 0       Tx 512-1023 Bytes: 222
    Rx 1024- Bytes:       4       Tx 1024- Bytes: 24

    Receive Error Counters     Transmit Error Counters
    ----------------------                -----------------------
    Rx CRC/Alignment:   0      Tx Collisions: 0
    Rx Undersize:           0      Tx Drops:        0
    Rx Oversize:             0      Tx Overflow:   0
    Rx Fragments:          0      Tx Aged:         0
    Rx Jabbers:              0      Tx -                  -
    Rx Drops:                 0      Tx -                  -
    Rx Classifier Drops: 0      Tx -                  -

    The pings do not pass and the Wireshark software visualizes weird frames

    why the ping does not pass ?


    Why am I getting weird frames ?

    Johann

  • Hi Johann,

    Were you able to get the 1G link working? I am not too familiar with wireshark and the ping test however it could be more on a software related issue if you see the PHY creating a physical link now.

    Thanks,

    Cecilia

  • The trick is to activate the auto-neg on the copper side and to deactivate the auto-neg on the SGMII side, then indicate to the PHy that its minimum speed is 1 Gbps by disabling the 10/100 Mbps.

    This trick makes it possible to force the SGMII link therefore to do without the management bus between the switch and the phy, then to indicate to the phy that it has only one possible speed in copper side autoneg, which amounts to forcing the link in 1Gbps.

    DP83867  0x001F 0x8000
    DP83867  0x0014 0x2907 
    DP83867  0x0004 0x0801
    DP83867  0x0009 0x1B00
    DP83867  0x0031 0x1030 
    DP83867  0x001F 0x4000

    Johann