DS90UH948-Q1: D_GPIO config

Roy Chou1

Part Number: DS90UH948-Q1

Hi Team,

I read the UH948 datasheet to understand the DGPIO setting. Could you let me know if I have any misunderstand in below points.

1. DGPIO only could use in 2-lane FPD link.

2. GPIO and DGPIO are pair setting. I mean that GPIO3 direction setting should be the same as D_GPIO3.

3. 7.3.9.1 table2 means the direction setting of GPIO/D_GPIO. If I set (947)0x0D[3:0]=0x3 and (948)0x1D[3:0]=0x5, does it mean that the 947 D_GPIO0 is an input and D_GPIO1 is an output?

4. If I set (947)0x0D[3:0]=0x3 and (948)0x1D[3:0]=0x5, And I use hardware to set 947's D_GPIO0 high and 948's D_GPIO0 will follow the 947 D_GPIO0, is it right?

5. Instead of use hardware method to set the pin high or low, could we use the register to set input state and then output follow the input?

6. Do we have register to know the D_GPIO output state?(ex. forward 947 to 948, if 947D_GPIO0 is high, 948D_GPIO0 will be high, do we have register to know the 947D_GPIO0 and 948D_GPIO0 state?)

Thank you for your support.

Regard,

Roy

over 5 years ago

0 Bryan Kahler over 5 years ago

TI__Mastermind 25955 points

Hi Roy,

1. Yes, DGPIO utilize TX1, so 2 lanes are required.

2. GPIO3 and D_GPIO3 use the same register to configure their settings, however, to configure D_GPIO set PORT1_SEL first to modify the settings for D_GPIO3 at 0x1F.

3. Yes, but make sure to set PORT1_SEL to modify the D_GPIO.

4. Yes, please let us know if you run into any issues.

5. With the 948, In register 0x1F (Bit 3:GPIO3_OUTPUT_VALUE _D_GPIO3_OUTPUT_VALUE) The value programmed will be output on the pin, however, this is local and will not follow the input of another pin.

6. No, however, the pin could be tied to another GPIO pin and read as an input.

Sincerely,
Bryan Kahler

0 Roy Chou1 over 5 years ago in reply to Bryan Kahler

TI__Genius 16110 points

Hi Bryan,

Thank you for your comments. I still have question on point #2 and #6.

I see default value of 0x34[1:0] = 01, does it mean if we would like to set GPIO3/D_GPIO3 in forward channel. We should set 0x0F[3:0]=0x3 first and then write 0x34[1:0] = 10, and then set 0x1F[3:0]=0x5, is it right?

Do you mean that if we set GPIO3/D_GPIO3 ->

0x0F[3:0] = 0x3 (after 0x34[1:0] = 01)
0x1F[3:0] = 0x5 (after 0x34[1:0] = 10)

And then we tied the 948 D_GPIO3 pin to 948 GPIO2 and write 0x1E[7:4]=0x3(after 0x34[1:0] = 10) and read 0x6E[2], is it right?

And if we use GPIO0(947) to GPIO0(948) – forward channel, we could we 0x6E to know the GPIO(948) status, is it right?

Regards,

Roy

0 Bryan Kahler over 5 years ago in reply to Roy Chou1

TI__Mastermind 25955 points

Hi Roy,

1) Yes, this is the correct train of thought. Please let me know if you run into issues when implementing these steps.

2) A second GPIO on the 948 may be set as an input and physically tied to the first output GPIO to monitor its state. This could then be brought back to the 947 pins via another GPIO.

947 948
GPIOX Input ---------> GPIOY Output
|
GPION Output <-------- GPIOM Input

I hope the ascii art diagram helps clear this up!

Sincerely,
Bryan Kahler

0 Roy Chou1 over 5 years ago in reply to Bryan Kahler

TI__Genius 16110 points

Hi Bryan,

Thank you for your detailed comments. It's helpful.

Last question : Does 0x6E this register could see the GPIO pin status(high=1 or low=0) if we set this GPIO pin is an input?

Regards,

Roy

0 Bryan Kahler over 5 years ago in reply to Roy Chou1

TI__Mastermind 25955 points

Hi Roy,

Yes, if set as an input.

Sincerely,
Bryan Kahler

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DS90UH948-Q1: D_GPIO config