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DP83822I: DP83822I timing issue for MDIO and RGMII

GW
Intellectual 2370 points
Part Number: DP83822I
Other Parts Discussed in Thread: DP83822EVM

Hi, Team

My customer using DP83822I in their smart speaker speaker, and they found that the MDIO and RGMII timing requirement can't match our datasheet. 

Could u help to check and give some suggestions?

1, MDIO: T1 "MDC to MDIO(Output) Delay Time" needs to support <=10ns base on our datasheet, but the test result is 11.6ns. For more detail pls check attachment  "MDIO timing issue.xlsx" 

2, RGMII: the rise/falling time of RX_CLK and RX-D can not match our datasheet spec, the spec is Tf/Tf is 0.75nS, but the test result is  1.54-1.66ns. For more detail pls check attachment "RGMII timing issue.xlsx"

3, They using our DP83822EVM  connect their system RGMII to our EVM, and found our EVM RGMII rise/fall time is also fail. Pls check "DP83822 EVM  RGMII.xlsx"

Could u help to confirm whether the "fail" timing is correct or not? How improve the performance? BTW, the test point is near the pin of DP83822.

Thanks.

G.W

MDIO timing issue.xlsx

RGMII timing issue.xlsx

DP83822 EVM RGMII.xlsx

  • 0
    TI__Genius 16030 points

    Hi G.W,

    A few things :

    1. All outputs of the phy should be measured close to the end points and not close to the phy (MDIO, rgmii). For rx_clk is the output of the phy and its rise-fall time should be checked at test point very close to the MAC. Otherwise reflections can distort the rise/fall time.

    2. Rise/fall time depends upon the load on the trace. And rgmii spec is for 5pF load.

    3. As Rgmii spec is for 125MHz data rate but for 100mbps 822 phy the clock rate for rgmii is 25MHz only. So system has lot of extra margin even if loading is high.

    4. What is the rise time of MDIO?

    --

    Regards,

    Vikram