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TL16C750E: CS hold time - Datasheet inconsistency

franziskus
Expert 8639 points

Part Number: TL16C750E

Team,

the datasheet of TL16C750E shows a hold time for the CS signal (page 11, figure 4). This is marked in the screenshot below.
The second data access in the same figure shows a different CS signal without hold time.

Can you clarify?

Thanks

  • 0
    TI__Guru* 78241 points

    When the mode pin is set to VCC, the device uses combinational logic to tell when a read/write request occurs by looking to see if two inputs are low (IOR && CS or IOW && CS). It doesn't matter which pins goes low first and which is released first, as long as both IOR/IOW and CS are low for the required time (t7w in this case). t6h how quickly you can change the address after either IOR or CS begin to go high. (Meaning which ever one goes high first does not matter).

    -Bobby