Dear ALl,
We have a custom board design wirh DP83867IR and Zynq MPSoC FPGA,
We have followed the refernce design of FPGA which has DP83867IR,
On out custom board, we are able to transfer and receive data through ethernet on 100M link,
1G link is not establishing,
Chip is configured in auto negotiation mode through Strap settings,
kindly help us in resolving the issue