Hi TI,
I am using the DS110DF410EVK evaluation board with a clock input directly from a coax of 644.3125MHz. From this I am trying to generate a 10.3125GHz PRBS 31 pattern.
Presently I can see that there is an input successfully (RX0A/RX0B) coming into the board on channel 0 and I can see a PRBS pattern out from the output on channel 0 (TX0A/TX0B) that is in the range of 10.3125GHz.
However the CDR is not locking and register 0x02 has value of 0x0 and the green locking LEDs on the PCB for channel 0 are not asserted.
Please could you advise on what registers I should be setting to get the CDR to lock?
The registers that are being set are:
"
Ds10df410ProgramListEntry_t programTable[] = {
{0x61, 0xB2, 0xFF}, /* Setting value of PPM count. */
{0x62, 0x00, 0xFF}, /* Setting value of PPM count. */
{0x63, 0xB2, 0xFF}, /* Setting value of PPM count. */
{0x64, 0xFF, 0xFF}, /* Setting value of PPM tolerance. */
{0x0C, 0x00, 0x08}, /* Turn Single Bit Limit Check Off */
{0x09, 0x04, 0x04}, /* Enable divsel override */
{0x18, 0x00, 0x70}, /* Select Divide by 1 */
{0x30, 0x00, 0x0F}, /* Disable PRBS Gen */
{0x1E, 0x00, 0xE0}, /* Select PRBS Gen */
{0x09, 0x20, 0x20}, /* Enable Mux Override */
{0x1E, 0x80, 0xE0}, /* Select PRBS Gen */
{0x1E, 0x10, 0x10}, /* Powerup PRBS Gen Analog */
{0x79, 0x20, 0x60}, /* Enable PRBS generator and disable PRBS checker */
{0x30, 0x0B, 0x0F}, /* Powerup PRBS Clk and select PRBS31 */
{0x0A, 0x0C, 0x0C}, /* Setting bits 3:2 */
{0x0A, 0x00, 0x0C}, /* Setting bits 3:2 */
};
"
And the subsequent output when these registers are pinged is:
"Shared registers:
SMBUS_ADDRESS_VALUE = 0x00
VERSION_VALUE = 0xf0 (expect 0xf0)
Channel 0 registers:
RESET_VALUE (0) = 0x00:
Core State Machine: Normal Operation
Channel registers: Normal Operation
Reference clock domain: Normal Operation
VCO DIV clock domain: Normal Operation
LOCK_LOSS_VALUE (1) = 0x00:
CDR_STATUS (2) = 0x00:
PPM Count met = 0 (PPM Tolerance exceeded)
CTLE Auto Adept Complete = 0 (in progress)
Fail Lock Check = 0 (signal quality and amplitude level not sufficient for CDR lock)
Lock = 0
CDR Lock = 0
Single Bit Limit Reached = 0
Comp LPF High = 0
Comp LPF Low = 0
REGISTER 3: 0x60
REGISTER 8: 0x00
REGISTER 9: 0x24
REGISTER 0xA: 0x10
REGISTER 0xB: 0x0f
REGISTER 0xC: 0x00
REGISTER 0xD: 0x00
REGISTER 0xE: 0x93
REGISTER 0xF: 0x69
REGISTER 0x10: 0x3a
REGISTER 0x11: 0x20
REGISTER 0x12: 0xa0
REGISTER 0x13: 0x30
REGISTER 0x14: 0x00
REGISTER 0x15: 0x10
REGISTER 0x16: 0x7a
REGISTER 0x17: 0x36
REGISTER 0x18: 0x00
REGISTER 0x19: 0x23
REGISTER 0x1A: 0x00
REGISTER 0x1B: 0x03
REGISTER 0x1C: 0x24
REGISTER 0x1D: 0x00
REGISTER 0x1E: 0x99
REGISTER 0x1F: 0x55
REGISTER 0x20: 0x00
REGISTER 0x21: 0x00
REGISTER 0x22: 0x00
REGISTER 0x23: 0x40
REGISTER 0x24: 0x40
REGISTER 0x25: 0x00
REGISTER 0x26: 0x00
REGISTER 0x27: 0x00
REGISTER 0x28: 0x00
REGISTER 0x29: 0x00
REGISTER 0x2A: 0x30
REGISTER 0x2B: 0x00
REGISTER 0x2C: 0x72
REGISTER 0x2D: 0x80
REGISTER 0x2E: 0x00
REGISTER 0x2F: 0x06
REGISTER 0x30: 0x0b
REGISTER 0x31: 0x20
REGISTER 0x32: 0x11
REGISTER 0x33: 0x88
REGISTER 0x34: 0xbf
REGISTER 0x35: 0x1f
REGISTER 0x36: 0x31
REGISTER 0x37: 0x0e
REGISTER 0x38: 0x00
REGISTER 0x39: 0x00
REGISTER 0x3A: 0xa5
REGISTER 0x3E: 0x80
REGISTER 0x60: 0x00
REGISTER 0x61: 0xb2
REGISTER 0x62: 0x00
REGISTER 0x63: 0xb2
REGISTER 0x64: 0xff
REGISTER 0x67: 0x20
REGISTER 0x69: 0x0a
REGISTER 0x6A: 0x44
REGISTER 0x6B: 0x00
REGISTER 0x6C: 0x00
REGISTER 0x6D: 0x00
REGISTER 0x6E: 0x00
REGISTER 0x70: 0x03
REGISTER 0x71: 0x20
REGISTER 0x72: 0x00
REGISTER 0x73: 0x00
REGISTER 0x74: 0x00
REGISTER 0x75: 0x00
"
Please can you advise on how to have the CDR lock to the signal?
Best regards,
Sean Suttie.
