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DS90UB941AS-Q1: query for the tearing issue in TI 941 ~ TI 948

Part Number: DS90UB941AS-Q1

Hi TI, 

I have a question for tearing issue in our system.

it uses: 

( host ) + (TI 941) -----------  (TI 948) + (Panel #1)

                                  └----- (TI 948) + (Panel #2) 

but, we have tearing issue both 2x output panel #1, #2. 

like this : https://www.google.com/search?q=tearing&source=lnms&tbm=isch&sa=X&ved=2ahUKEwjU6tv33MzqAhVbyYsBHR_FCEwQ_AUoAXoECBQQAw&biw=1774&bih=989#imgrc=rg7uliEGLRBNjM

and now I am checking on TI 941 and TI 948 for debug or related register.

we use splitting mode in TI 941 (1x 2560x720) for 2x TI 948. (each 1280x720)

and here are questions : 

q1) Is there any clock relation to check in TI 941 ?? 

and is there any register to set the operating or pixel clock ?? 

q2) is there any check point in TI 941 or TI 948 ? let me know the guide. 

Regards, 

  • Hi Minwoo,

    Is this screen tearing a persistent issue? will the screen tear in the same place every time? How often does it occur? What SOC are you using? does it occur if the images on the screen are still?

    What clocking mode are you using on the 941? are you using evem/odd splitting or Left/right?

    Regards,

    Michael W.

  • Hi Michael W.,

    I answered inline comment below : 

    Is this screen tearing a persistent issue? 

    => [7/15 MW] yes persistent, I guess, when I use simple image like white and block screen, it shows every time, of course, the location in image is a little changed. (not fixed location)

    will the screen tear in the same place every time? How often does it occur? 

    => [7/15 MW]  not same place, it changed a little within some lines. (up and down) 

    What SOC are you using? 

    => [7/15 MW]  SoC is not TI's. of course, we are checking on AP inside operation aspect. 

    does it occur if the images on the screen are still?

    => [7/15 MW] when we use Pattern gen image (fixed image), we can't see tearing issue, we only can see motion-images.

    What clocking mode are you using on the 941? are you using evem/odd splitting or Left/right?

    => [7/15 MW] we use split Left / Right. 

    Thanks 

  • Hi Minwoo,

    Is the CLK source the DSI clk or the REFCLK? if the clk source is the DSI clk is it in continuous or discontinuous? What are your DSI driver settings? are both panels the same? Can you send the panel datasheet timing requirements?

    Regards,

    Michael W.

  • Hi Michael. 

    Here is answer below:

    for timing information, I will ask to our SW engineer. but each panel resolution is 1280x720 (or 800). 

    DSI clock source is from Host AP. and its clock mode is continuous. 

    for DSI driver setting, both panels are same. 

    Regards.  

  • Hi Minwoo,

    Can you please talk to your software engineer and make sure that the blanking is correct to what the panel datasheet requires.

    Regards,

    Michael W.

  • Hi, 

    Thanks Michael, 

    I will check and ask to SW engineer for blank timing issue. 

    and if problem is remained, I will ask again.

    Regards,

  • Hi Minwoo,

    Any updates?

    Regards,

    Michael W.

  • Hi Michael.

    Very thanks for your concern. 

    I asked for blank timing issue and additional debugging to SW engineer. 

    and I heard that, that was App issue to control image SoC internally.

    Of course, he also re-checked the timing setting at the same time. 

    but it's remained and we are checking on input path of Host SoC together. 

    I will update it when I might meet the meaningful result. 

    Thanks