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SN65LVDT2: Operation at 2.5V

John Garrett
Expert 4220 points

Part Number: SN65LVDT2

Hi All,

 

Hope you are well. I have a question about the SN65LVDT2DBVT. The transceiver is used on a current design where the differential input clock is a 125MHz, 3.3 LVCMOS signal. The VCC of this transceiver is at 3.3V as well. The output LVTTL signal feeds a device at a 2.5 V logic level with a max input voltage of 2.8 V. It appears to be working on this previous generation design, though in theory it looks like it shouldn't. 

 

What is the best solution for the next generation of this design:

1. Would the best approach be to power the transceiver with a 2.5V maybe a 2.7V supply so as to ensure that the output TTL signal is at the required voltage level. Would the input clock need a level shifter ? I am assuming it wont as the minimum input voltage on the transceiver is met .

2. Does it make more sense to level shift the output. 

After reviewing the data sheet it seems like option 1 is feasible.  Please confirm.

 

Thanks,

John Garrett

TI-AFA