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SN65DPHY440SS: Asking for the SN65DPHY440SS design suggestion

SHH
Mastermind 32416 points

Part Number: SN65DPHY440SS

 Hi Sir,

 

My customer would like design SN65DPHY440SS to enhance mage sensor MIPI signal after a long FPC.

There are 2 questions about  SN65DPHY440SS. Please provide your comments.

1. The image sensor interface is CSI-2, can we swap the lane to make the layout smooth? ex: connect sensor lane0 to SN65DPHY440SS DA1, lane2 to DA0.

Customer saw the LP mode at datasheet 7.4.2, but it is for DSI, so customer want to confirm that SN65DPHY440SS can swap lanes when the sensor interface is CSI-2. 

2. About I2C, customer saw the description in section 7.5: "Access to the CSR registers is supported during ultra-low power state (ULPS)", but according to 7.4.3, ULPS mode can only be entered from LP Mode.

Does it mean that the design can't use I2C when we use CSI interface?

 

 

BR,

SHH

  • 0
    TI__Guru**** 183821 points

    SHH

    1. SN65DPHY440 supports lane swap in CSI-2 application as long as the lane order is the same between the input and the output. Please note ​DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0. 

    2. I2C access can still be supported in the CSI-2 application.

    Thanks

    David