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SN75DPHY440SS: wiring length and mounting position

user3964028
Prodigy 120 points
Part Number: SN75DPHY440SS

Hi,

I would use SN75DPHY440SS, and  I have two questions.

the conditions are 1600x1200 , 20fps , output format:YCbCr4:2:2, MIPI-CSI 2lane

Q1）

Is there a rule of thumb that the DPHY440 should be used when the length of the cable (1) or the wiring length L from the camera to the MPU is more than  XXX centimeters?

Or, with the resolution and frame rate of the camera used this time, the datarate is 307.2Mbps/lane, and it is not so high, so is  there  no necessity to use DPHY440?

Frequency calculation

the conditions are 1600x1200 2byte/pix 20fps

1600x1200x2x20x8=614.4Mbps

the num of data lane is  2

614.4Mpbs/2=307.2Mbps/lane

mipi clock is DDR 

307.2/2=153.6MHz

Q2）

In the case of the  configuration,My Application, which should be the mounting position of DPHY440,  A position or B position?

Is it the position of A from the figure of  "Typical Application" described in the data sheet sn75dphy440ss.pdf?

  • 0
    TI__Guru**** 165681 points

    Hi,

    A1. The DPHY1.2 spec defines channel conditions in section 8.6.1 which a DPHY compliant receiver must support. 

    1. Do you know if the total channel loss meets the DPHY 1.2 SDD21 mask?  

    2. Is the MPU RX a DPHY compliant RX or what is its actual RX performance?

    Answering these two questions would help determining whether the DPHY440 is needed or not.

    A2. You would want to put the DPHY440 in position A to maximize the DPHY440 RX as much as possible. Please make sure the cable to the DPHY440 RX meets the DPHY440 setup/hold timing requirement.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 120 points

    Hi David!

    Thank you for your reply.

    A2
    I will put the DPHY440 in position A.

    A1
    >2. Is the MPU RX a DPHY compliant RX or what is its actual RX performance?
    The MPU complies with MIPI Alliance Specification for DPHY v1.2


    >1. Do you know if the total channel loss meets the DPHY 1.2 SDD21 mask?

    I found this site,caxapa.ru/.../mipi_D_PHY_specification_v1_2.pdf,
    and "8.6.1 Differential Characteristics, Figure 31 Template for Differential Insertion Losses, Data Rates <= 1.5 Gbps" in it.



    My understanding is that DPHY440 is NOT needed in area (a),
    and DPHY440 is needed in areas other than (a).

    But I don't know how to confirm that the total channel loss meets the mask.

    Do you have any simulation tools?
    Or do I need to measure the signal with an measuring equipment such as oscilloscope, network analyzer, spectrum analyzer?
    But I don't have a PCB yet. now I am designing  the circuit.


    Could you please tell me the steps that I have to do?

    step1 : .....
    step2 : .....
    step3 : .....

    Regards

  • 0 in reply to user3964028
    TI__Guru**** 165681 points

    Hi,

    The estimated total loss = Cable 2 + Cable 2 connector + PCB.B loss + PCB.B Cable 1 connector + Cable 1 + PCB.A Cable 1 connector + PCB.A loss to the DPHY440.

    PCB.A and PCB.B loss would include trace, via and other board related loss with the trace loss being the bigger factor.

    You would have to check with the connector and cable vendor to get the loss information from them. 

    For the PCB loss, you can use this formula to estimate the loss per inch.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 120 points

    Hi David

    Thank you for your informaiton.

    Regards