Other Parts Discussed in Thread: DS90UB913A-Q1
Hello Expert,
(1). Do you know any method to know whether DS90UB954-Q1 RX Port is configured as "RAW12 HF" successfully ?
(2). Our System Architecture => AR0135 -> DS90ub913A-Q1 -> DS90UB954-Q1 -> NXP i.MX8MM
We follow 7.5.11.4 to generate DS90UB954-Q1's Test Pattern to our Host (NXP i.Mx8MM).
==========================================================================
err = regmap_write(priv->de_data.regmap, 0x4c, 0x01); //# FPD3_PORT_SEL
err = regmap_write(priv->de_data.regmap, 0x58, 0x58); //# BCC_CONFIG
err = regmap_write(priv->de_data.regmap, 0x6d, 0x7e); //# (INPUT) PORT_CONFIG
err = regmap_write(priv->de_data.regmap, 0x5c, 0xb4); //# SER_ALIAS_ID
err = regmap_write(priv->de_data.regmap, 0x5d, 0x20); //# SlaveID[0]
err = regmap_write(priv->de_data.regmap, 0x65, 0x20); //# SlaveAlias[0]
err = regmap_write(priv->de_data.regmap, 0x20, 0x20); //# FWD_CTL1
//Output
err = regmap_write(priv->de_data.regmap, 0x32, 0x01); //# CSI_PORT_SEL
err = regmap_write(priv->de_data.regmap, 0x33, 0x21); //# CSI_CTL: 2 lanes
err = regmap_write(priv->de_data.regmap, 0x1f, 0x02); //# CSI_PLL_CTL: 800 Mbps serial rate
err = regmap_write(priv->de_data.regmap, 0x71, 0x2c); //# RAW12_ID
err = regmap_write(priv->de_data.regmap, 0xbc, 0x00); //# FRAME_VALID_MIN
//Test Pattern 1280x720P30
regmap_write(priv->de_data.regmap, 0xB0,0x00); //# Indirect Pattern Gen Registers
regmap_write(priv->de_data.regmap, 0xB1,0x01); //# PGEN_CTL
regmap_write(priv->de_data.regmap, 0xB2,0x01);
regmap_write(priv->de_data.regmap, 0xB1,0x02); //# PGEN_CFG
regmap_write(priv->de_data.regmap, 0xB2,0x33);
regmap_write(priv->de_data.regmap, 0xB1,0x03); //# PGEN_CSI_DI
regmap_write(priv->de_data.regmap, 0xB2,0x2C); //# RAW12
regmap_write(priv->de_data.regmap, 0xB1,0x04); //# PGEN_LINE_SIZE1
regmap_write(priv->de_data.regmap, 0xB2,0x0F);
regmap_write(priv->de_data.regmap, 0xB1,0x05); //# PGEN_LINE_SIZE0
regmap_write(priv->de_data.regmap, 0xB2,0x00);
regmap_write(priv->de_data.regmap, 0xB1,0x06); //# PGEN_BAR_SIZE1
regmap_write(priv->de_data.regmap, 0xB2,0x01);
regmap_write(priv->de_data.regmap, 0xB1,0x07); //# PGEN_BAR_SIZE0
regmap_write(priv->de_data.regmap, 0xB2,0xE0);
regmap_write(priv->de_data.regmap, 0xB1,0x08); //# PGEN_ACT_LPF1
regmap_write(priv->de_data.regmap, 0xB2,0x02);
regmap_write(priv->de_data.regmap, 0xB1,0x09); //# PGEN_ACT_LPF0
regmap_write(priv->de_data.regmap, 0xB2,0xD0);
regmap_write(priv->de_data.regmap, 0xB1,0x0A); //# PGEN_TOT_LPF1
regmap_write(priv->de_data.regmap, 0xB2,0x04);
regmap_write(priv->de_data.regmap, 0xB1,0x0B); //# PGEN_TOT_LPF0
regmap_write(priv->de_data.regmap, 0xB2,0x1A);
regmap_write(priv->de_data.regmap, 0xB1,0x0C); //# PGEN_LINE_PD1
regmap_write(priv->de_data.regmap, 0xB2,0x0C);
regmap_write(priv->de_data.regmap, 0xB1,0x0D); //# PGEN_LINE_PD0
regmap_write(priv->de_data.regmap, 0xB2,0x67);
regmap_write(priv->de_data.regmap, 0xB1,0x0E); //# PGEN_VBP
regmap_write(priv->de_data.regmap, 0xB2,0x21);
regmap_write(priv->de_data.regmap, 0xB1,0x0F); //# PGEN_VFP
regmap_write(priv->de_data.regmap, 0xB2,0x0A);
==========================================================================
Could you help us to confirm whether the attached est Pattern is correct ? We assume it is RAW12, Bayer BGGR format)
(by using "ffplay.exe -video_size 1280x720 -pixel_format bayer_bggr16le output.rgb")
Thanks for your help.
Sincerely,
TC.Chou