DS90UB941AS-Q1: How to configure 941as register when pairing with DS90UB926-Q1?

Hi Yu Song,

Please provide a diagram showing the physical connections here.  Here is a basic example, please amend:

           941AS                               926
     __________________              ________________________        _________
DSI |                  |    FPD3    |                        |      |         |
--->|DSI0         DOUT0|------------|RIN0               TXOUT|------| DISPLAY |
    |__________________|            |________________________|      |_________|

Also, please let us know what your strap settings are for both the 941AS and the 926 devices (IDX, modesel, etc...).

Sincerely,
Bryan Kahler

Hi Bryan,

You can refer to the below diagram.  I want to know which registers will affect the HS/VS signal output? Thank you.

Best regards,

Yu

Hi Yu,

The diagram didn't load on this end.  Please try to reupload or modify the ASCII art version provided above.

Many registers can affect the HS/VS signal output.  First step here is to ensure the device is programmed as physically connected.  Then, lock is good.  Finally, timing is configured properly.

Sincerely,
Bryan Kahler

Hi Bryan,

Please see the system block diagram. 

Best regards,

Yu

Hi Yu,

Based on the diagram above, the connections should be handled with a single port configuration.

For Modsel[1:0] instead of splitter mode, strap for normal operation.

Normal + DSI Lanes

When strapped in this configuration, the device should lock when powered on.

Confirm lock.

After lock has been confirmed, use patgen using internal timing to test timing out on the 926.  Confirm you see the HS/VS/DE/RGB signals.

Modify timing values as needed with patgen to ensure proper color bars on the display.

After confirmation of all the above, please let me know and we will move on to bringing up the DSI interface.

Sincerely,
Bryan Kahler

Hi Bryan,

For Modsel[1:0] is correct, splitter=0.

In fact, the lock is normal now. And there are CLK, DATA and DE signals, but there is no HS and VS. What configuration is required for DSI on the 941 side? Thank you.

Best regards,

Yu

Hi Yu,

Excellent.  Have you confirmed proper timing using internal patgen? 

Please share the colorbar image on the display.

Sincerely,
Bryan Kahler

Hi Bryan,

Yes, using 926 internal pattern, the display works normally, but I didnot save picture. Could you help to share the example code from 941as side for this application?  Thanks.

Best regards,

Yu

Hi Yu,

As twice requested above, use 941AS as the patgen source.  Configure with ALP.  Confirm HS and VS signaling is proper.  These steps are critical to ensure there aren't downstream issues before tackling the DSI interface.

Sincerely,
Bryan Kahler

Hi Bryan，

I have tested internal pattern based on 941 and 926， it works normal, which means HS and VS signaling is proper. 

Regards,

Yu

Hi Yu,

Excellent.  Program your DSI settings with ALP.

With those settings, ensure your DSI clock is set to continuous and the device is configured to use the DSI clock.  Enable DSI.

Now in ALP switch patgen to use the external clock, internal timing.

Please confirm the display is still good using the DSI clock.

Sincerely,
Bryan Kahler