SN65DSI84-Q1: Is compatible with D-PHY 1.2 in SoC?

Lee, Sam

Part Number: SN65DSI84-Q1

Hi team,

Can you answer the following questions?

-. SN65DSI84-Q1(D-PHY1.0) is backward ompatible with D-PHY1.2 version in SoC?

-. Below is the vidoe format for two streams. Can SN65DSI84-Q1 support the spec with the D-PHY 1.2 TX of SoC?

Video output : overhead 35%, Blank Interval: 1.35

1. 1920x720x60Hz / 24bpp => 2.687Gbps (w/ overhead)

2. 800x480x60Hx / 24bpp => 0.746Gbps (w/ overhead)

=> Total 3.434Gbps

Thanks,

Sam Lee

0 Ikechukwu Anyiam over 5 years ago

Hi Sam,

The SN65DSI84-Q1 can support each of those streams but not at the same time. It will only take in one input stream.

Regards,

I.K.

0 Lee, Sam over 5 years ago in reply to Ikechukwu Anyiam

Hi I.K.

Thank you for your reply. Can I ask additional questions?

1. “It will only take in one input stream.” means that SN65DSI8x-Q1 doesn’t support virtual channel? Is it because video pipe line is only one?

2. In datasheet, the example for dual mode is explained only for VESA timing. Is SN65DSI8x-Q1 also supporting JEIDA timing for the dual mode?

3. The LVDS pin swap is supported for A/B port swap and Reverse swap. However, is it possible to swap between Data/CLKs for Artwork optimization?

For example, B_Y0P -> B_Y3P is Reverse swap, but is it possible to map B_Y0P-> B_Y1P?

Thanks,

Best Regards,

Sam Lee

0 Ikechukwu Anyiam over 5 years ago in reply to Lee, Sam

Hi Sam,

1. Correct, the DSI8x does not support virtual channel.

2. Yes, see the "LVDS Output Formats" section.

3. No.

Regards,

I.K.

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