Other Parts Discussed in Thread: DS90UB953-Q1
We are debugging a project SENSOR IMX307 2LANE-> ds90ub953-> HOST
DS90UB954 IDX, MODE 10K against ground REFCLK:26MHZ.DS90UBDS90UB953 IDX 40.2K to ground.Using the 954 remote I2C
So our register address is configured as: TI954Q_WRITE_ID:0x60.TI953Q_WRITE_ID: 0 x30. TI953Q_WRITE_ALIAS_ID: 0X18
There is BIST Script running snla267a.pdf but there are some errors.
#define TI953Q_WRITE_ID 0x30
#define TI953Q_WRITE_ALIAS_ID 0x18
#define SEN_WRITE_ID 0x34
#define SEN_WRITE_ALIAS_ID 0x36
TI_WriteReg(TI954Q_WRITE_ID, 0x4C, 0x01); //Enable Port 0
//writes
TI_WriteReg(TI954Q_WRITE_ID, 0x58, 0xBE); //I2C Pass through 0x58 must be set to 0xBE, otherwise the I2C NACK of DS90UB953 will appear
//Enabled and BC = 50Mbps
TI_WriteReg(TI954Q_WRITE_ID, 0x5C, TI953Q_WRITE_ALIAS_ID<<1); //953 Alias defined
//as 0x18
//Digital Reset except for registers
TI_WriteReg(TI953Q_WRITE_ALIAS_ID, 0x01, 0x01); //Resets 953
Delay_DelayUs(500);
TI_WriteReg(TI954Q_WRITE_ID, 0x01, 0x01); //Resets 954
Delay_DelayUs(500);
debug_msg("Devices Reset\r\n");
//Confirm Devices can communicate with each other
debug_msg("954 Device ID (0x00):0x%x\r\n",TI_ReadReg(TI954Q_WRITE_ID,0x00)); //954 Device ID,
//should be 0x7A, check 0x00 for confirmation
Delay_DelayUs(500);
debug_msg("953 Device ID (0x00):0x%x\r\n",TI_ReadReg(TI953Q_WRITE_ALIAS_ID, 0x00)); //953 Device ID,
//should be 0x30, check 0x5B for confirmation
debug_msg("------------------------------------------------------------------\r\n");
Delay_DelayUs(500);
//Read Receiver Lock Status
debug_msg("954 Receiver Lock Status (0x04):0x%x\r\n", TI_ReadReg(TI954Q_WRITE_ID,0x04));
//0x04 is DEVICE_STS of 954
debug_msg("Should read 0xCF\r\n");
debug_msg("------------------------------------------------------------------\r\n");
Delay_DelayUs(500);
//Enable write for Port0 of FPD3_PORT_SEL
TI_WriteReg(TI954Q_WRITE_ID, 0x4C, 0x01); //0x4C is
//FPD3_PORT_SEL
//Clear Errors and Error Count
TI_WriteReg(TI953Q_WRITE_ALIAS_ID, 0x49, 0x28); //0x49 is BC_CTRL.
//0x28 selects BIST_CRC ERR CLR and CRC ERR CLR
//BCC_Error by Reading BCC Error Status
debug_msg("Consult Register 0x79 on the SER for more information\r\n");
debug_msg("------------------------------------------------------------------\r\n");
debug_msg("953 Pre Error Link Status of 953 (0x52):0x%x\r\n",TI_ReadReg(TI953Q_WRITE_ALIAS_ID, 0x52));//0x52 is
//GENERAL_STS of 953
debug_msg("Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect\r\n");
debug_msg("------------------------------------------------------------------\r\n");
debug_msg("953 BIST CRC Error count (0x54):0x%x on 953 before forced error.\r\n",TI_ReadReg(TI953Q_WRITE_ALIAS_ID, 0x54));//0x54 is BIST ERR CNT
debug_msg("------------------------------------------------------------------\r\n");
Delay_DelayUs(1000);
//Enabling BIST, Error, and Lock-Change Status
debug_msg("954 Read BIST CTL register (0xB3):0x%x Before BIST ENABlED\r\n",TI_ReadReg(TI954Q_WRITE_ID, 0xB3));//xB3 is BIST_CTL, bit 1 controls if enabled or not
debug_msg("Should read 0x00 or 0x08\r\n");
TI_WriteReg(TI954Q_WRITE_ID, 0xB3, 0x01);//Enable BIST using
//BIST_CTL
debug_msg("954 Read BIST CTL (0xB3):0x%x register After BIST ENABLED\r\n",TI_ReadReg(TI954Q_WRITE_ID, 0xB3));//0xB3 is BIST_CTL
debug_msg("Should read 0x01\r\n");
Delay_DelayUs(250);
debug_msg("------------------------------------------------------------------\r\n");
debug_msg("954 Read BIST Lock Status Change of 954 RIGHT AFTER BIST enabled (0x4D):0x%x \r\n",TI_ReadReg(TI954Q_WRITE_ID,0x4D));//0x4D is RX_PORT_STS1 of 954
debug_msg("Read to clear BIST enable Lock Status Change.\r\n");
TI_WriteReg(TI954Q_WRITE_ID, 0xD0, 0x01);//Force 1 Error, 0xD0
//is PORT_DEBUG register
TI_WriteReg(TI954Q_WRITE_ID, 0xD0, 0x02);//Force Continuous
//errors, 0xD0 is PORT_DEBUG register
Delay_DelayMs(10);//Can run BIST for
//as long as needed
TI_WriteReg(TI954Q_WRITE_ID, 0xD0, 0x00);//If forced
//continuous errors, stop forcing errors
debug_msg("954 Read Post BIST Lock Status Change of 954 RIGHT BEFORE BIST disabled (0x4D):0x%x\r\n",TI_ReadReg(TI954Q_WRITE_ID, 0x4D));//0x4D is RX_PORT_STS1 of 954
debug_msg("Should read 0x03, If lock status changed during BIST, will read 0x13\r\n");
//Disable BIST and Port0
TI_WriteReg(TI954Q_WRITE_ID, 0xB3, 0x00);//Disable BIST, using
//BIST_CTL
TI_WriteReg(TI954Q_WRITE_ID, 0x4C, 0x00);//0x4C is
//FPD3_PORT_SEL
debug_msg("------------------------------------------------------------------\r\n");
Delay_DelayMs(1);
//Check if Error(s) occurred
debug_msg("953 Post Error Link Status of 953 (0x52):0x%x\r\n", TI_ReadReg(TI953Q_WRITE_ALIAS_ID, 0x52));//0x52 is GENERAL_STS of 953
debug_msg("Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error\r\n");
debug_msg("954 Receiver Lock Status (0x04):0x%x\r\n",TI_ReadReg(TI954Q_WRITE_ID, 0x04));//0x04 is DEVICE_STS of 954
debug_msg("Should read 0xCF\r\n");
debug_msg("------------------------------------------------------------------\r\n");
debug_msg("953 BIST CRC Error count (0x54):0x%x on 953.\r\n",TI_ReadReg(TI953Q_WRITE_ALIAS_ID, 0x54));//0x54 is BIST
//ERR CNT
debug_msg("954 Parity Error count MSB (0x56):0x%x on 954.\r\n",TI_ReadReg(TI954Q_WRITE_ID, 0x56));//0x56 is
//number of Parity error 8 most significant bits
debug_msg("954 Parity Error count LSB (0x55):0x%x on 954.\r\n",TI_ReadReg(TI954Q_WRITE_ID, 0x55));//0x55 is
//number of Parity error 8 least significant bits
debug_msg("------------------------------------------------------------------\r\n");
debug_msg("953 Device ID (0x00)::0x%x\r\n", TI_ReadReg(TI953Q_WRITE_ALIAS_ID, 0x00));//953 Device ID,
//should be 0x30, check 0x5B for confirmation,
//Usually use this
//to see if 954 is stuck in BIST mode
//Clear BIST Errors on 953
TI_WriteReg(TI953Q_WRITE_ID, 0x49, 0x28);// #0x49 is BC_CTRL.
//0x28 selects BIST_CRC ERR CLR and CRC ERR CLR
Devices Reset
TI w_addr 0x60 Reg addr 0x00, data 0x60
954 Device ID (0x00):0x60
TI w_addr 0x18 Reg addr 0x00, data 0x18
953 Device ID (0x00):0x18
------------------------------------------------------------------
TI w_addr 0x60 Reg addr 0x04, data 0xDF
954 Receiver Lock Status (0x04):0xdf
Should read 0xCF
------------------------------------------------------------------
TI w_addr 0x18 Reg addr 0x79, data 0x18
953 Read BCC Error Status (0x79):0x18
Consult Register 0x79 on the SER for more information
------------------------------------------------------------------
TI w_addr 0x18 Reg addr 0x52, data 0x18
953 Pre Error Link Status of 953 (0x52):0x18
Should read 0x45 = RX Lock Detect, HS PLL Lock, Link Detect
------------------------------------------------------------------
TI w_addr 0x18 Reg addr 0x54, data 0x18
953 BIST CRC Error count (0x54):0x18 on 953 before forced error.
------------------------------------------------------------------
TI w_addr 0x60 Reg addr 0xB3, data 0x08
954 Read BIST CTL register (0xB3):0x8 Before BIST ENABlED
Should read 0x00 or 0x08
TI w_addr 0x60 Reg addr 0xB3, data 0x01
954 Read BIST CTL (0xB3):0x1 register After BIST ENABLED
Should read 0x01
------------------------------------------------------------------
TI w_addr 0x60 Reg addr 0x4D, data 0x17
954 Read BIST Lock Status Change of 954 RIGHT AFTER BIST enabled (0x4D):0x17
Read to clear BIST enable Lock Status Change.
TI w_addr 0x60 Reg addr 0x4D, data 0x07
954 Read Post BIST Lock Status Change of 954 RIGHT BEFORE BIST disabled (0x4D):0x7
Should read 0x03, If lock status changed during BIST, will read 0x13
------------------------------------------------------------------
TI w_addr 0x18 Reg addr 0x52, data 0x18
953 Post Error Link Status of 953 (0x52):0x18
Should read 0x4D = RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error
TI w_addr 0x60 Reg addr 0x04, data 0xDF
954 Receiver Lock Status (0x04):0xdf
Should read 0xCF
------------------------------------------------------------------
TI w_addr 0x18 Reg addr 0x54, data 0x18
953 BIST CRC Error count (0x54):0x18 on 953.
TI w_addr 0x60 Reg addr 0x56, data 0xFF
954 Parity Error count MSB (0x56):0xff on 954.
TI w_addr 0x60 Reg addr 0x55, data 0xFF
954 Parity Error count LSB (0x55):0xff on 954.
------------------------------------------------------------------
TI w_addr 0x18 Reg addr 0x00, data 0x18
953 Device ID (0x00)::0x18
--------------------------------end---------------------------
1. Are our TI954Q_WRITE_ID, TI953Q_WRITE_ID, TI953Q_WRITE_ALIAS_ID set correctly?
2. At present, DS90UB953 ReadReg is all address value, why?What need to be verified.