Other Parts Discussed in Thread: SN65DP159
Hi,
We would like to be able to test the HDMI input to our Xilinx FPGA that uses the TI TMDS181 chip. From the TI datasheet:
8.3.5 TMDS Inputs Debug Tools
There are two methods for debugging a system to make sure the inputs to the TMDS181 are valid. A TMDS
error checker is implemented to provide a rough bit error rate per data lane. This allows the system implementer
to determine how the link between the source and TMDS181 is performing on all three data lanes. See RX
PATTERN VERIFIER CONTROL/STATUS Register.
If a high error count is evident, the TMDS181 has a way to view the general eye quality. A tool is available that
uses the I2C link to download the data that can be plotted for an eye diagram. This is available per data lane.
This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal on the
data pins. A clock at the proper frequency is required on the IN_CLK pins to generate the expected output data
rate.
I looked at the RX PATTERN VERIFIER CONTROL/STATUS Register and it looks like some king of PBRS test is available. I
would like to get more information about this. It would be more convenient if we could test this in production without
have to test the complete datapath of the FPGA.
