Connection Issues Between 954 and 913

JINWOOK CHOI

Prodigy 20 points

Part Number: DS90UB954-Q1

No problem with the LOCK in the Deserializer. But 954 MIPI DATA OUTPUT is abnormal.

Could you check if there is anything wrong with the setting below?

SENSOR OUTPUT

RAW 12 BIT / PCLK 54MHz / MCLK 27MHz / 25fps

954 Setting Value(0x30)

0x0D 0xB0
0x0C 0x81

0x20 0x20
0x1F 0x02

0x4C 0x01
0x58 0x58
0x7C 0x01
0x6D 0x7E

0x4C 0x01

// I2C Alias Port0
0x5B 0xB0 // Write SER Origianl address
0x5C 0xB0 // Write SER Changing address
0x5D 0x20 // Write SENSOR Original address
0x65 0x20 // Write SENSOR Changing address
0x5E 0x14 // Write PMIC Original address
0x66 0x14 // Write PMIC Changing address
0x5F 0xA2 // Write EEPROM Original address
0x67 0xA2 // Write EEPROM Changing address

// FPD RAW12 Virtual Channel
0x4C 0x01 // FPD RX0 Port Config
0x71 0x2C // VC0 ID

0x4C 0x01 // FPD Port Config

0xbc 0xc3

sleep 20

0x6E 0x98

0x33 0x01 // MIPI CSI Port0 Enable, 4Lane

913 Setting Value(0x58)

0x05 0x1a

0x03 0xc5

over 5 years ago

0 Carrie Kemmet over 5 years ago

TI__Intellectual 1025 points

Hello Jinwook,

Your register configuration looks fine. What value do you read from the TX_PORT_PASS bit in register 0x35 of the 954? This information will help narrow down the source of the issue.

I've attached a script for enabling the pattern generator of the 954 in RAW12 mode (800 Mbps CSI lane rate). Let me know you see normal output with this or not.

Regards,

Carrie

Fullscreen 954_CSI_patgen_RAW12_1280x720p30.txt Download

"""
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"""
# CSI patgen                 
# Python script CSI_patgen_RAW12_1280x720p30
# Version 0.91                

# CSI cont clk and CSI enable                           
# board.WriteReg(0x32, 0x01)                            
board.WriteReg(0x33, 0x03)                 
   
board.WriteReg(0xB0, 0x02)                # IA_AUTO_INC=1
board.WriteReg(0xB1, 0x01)                # PGEN_CTL
  
board.WriteReg(0xB2, 0x01)                # PGEN_ENABLE=1
board.WriteReg(0xB2, 0x33)                # PGEN_CFG
board.WriteReg(0xB2, 0x2C)                # PGEN_CSI_DI
board.WriteReg(0xB2, 0x07)                # PGEN_LINE_SIZE1
board.WriteReg(0xB2, 0x80)                # PGEN_LINE_SIZE0
board.WriteReg(0xB2, 0x00)                # PGEN_BAR_SIZE1
board.WriteReg(0xB2, 0xF0)                # PGEN_BAR_SIZE0
board.WriteReg(0xB2, 0x02)                # PGEN_ACT_LPF1
board.WriteReg(0xB2, 0xD0)                # PGEN_ACT_LPF0
board.WriteReg(0xB2, 0x03)                # PGEN_TOT_LPF1
board.WriteReg(0xB2, 0x20)                # PGEN_TOT_LPF0
board.WriteReg(0xB2, 0x10)                # PGEN_LINE_PD1
board.WriteReg(0xB2, 0x47)                # PGEN_LINE_PD0
board.WriteReg(0xB2, 0x0A)                # PGEN_VBP
board.WriteReg(0xB2, 0x0A)                # PGEN_VFP
board.WriteReg(0xB2, 0xAA)                # PGEN_COLOR0
board.WriteReg(0xB2, 0x33)                # PGEN_COLOR1
board.WriteReg(0xB2, 0xF0)                # PGEN_COLOR2
board.WriteReg(0xB2, 0x7F)                # PGEN_COLOR3
board.WriteReg(0xB2, 0x55)                # PGEN_COLOR4
board.WriteReg(0xB2, 0xCC)                # PGEN_COLOR5
board.WriteReg(0xB2, 0x0F)                # PGEN_COLOR6
board.WriteReg(0xB2, 0x80)                # PGEN_COLOR7
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR8
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR9
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR10
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR11
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR12
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR13
board.WriteReg(0xB2, 0x00)                # PGEN_COLOR14
board.WriteReg(0xB2, 0x00)                # Reserved

0 JINWOOK CHOI over 5 years ago in reply to Carrie Kemmet

Prodigy 20 points

Hello Carrie Kemmet,

Your register configuration looks fine. What value do you read from the TX_PORT_PASS bit in register 0x35 of the 954? This information will help narrow down the source of the issue.

-> When i read 0x35 of the 954, the value is 0.

I've attached a script for enabling the pattern generator of the 954 in RAW12 mode (800 Mbps CSI lane rate). Let me know you see normal output with this or not.

-> the pattern generator is OK.

And we use coaxial connetion.

0 Carrie Kemmet over 5 years ago in reply to JINWOOK CHOI

TI__Intellectual 1025 points

Hello Jinwook,

Please send a register dump for both devices, so I can review your configuration.

Regards,

Carrie

Interface

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Connection Issues Between 954 and 913