Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 32 subscribers
  • Views 1022 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: MDI repeater with back to back SGMII connection

Luka Kosanovic
Prodigy 50 points
Part Number: DP83867E
Other Parts Discussed in Thread: DP83869,

Hello, I am developing a simple 10/100/1000 repeater and your DP83867 gigabit ethernet PHY has caught my eye as a potentially good solution to this problem. My goal would be to connect the 2 PHY chips with SGMII back to back. The reason for using SGMII is I would in the second phase of the project connect a simple LVDS fanout buffer to RX and TX SGMII line so I can monitor the traffic in each direction.

My questions are:

I would need a confirmation is this possible using DP83867, or maybe DP83869 is better for this job (I need the latency to be lowest possible)?

I have read that SGMII auto-negotiation can pose a problem, is it possible to overcome this problem by setting one PHY as master, and the other one as slave (it is important for me to have 10/100/1000 MDI capability)?

Regarding the traffic monitoring feature, is it possible to route outputs of the LVDS fanout buffer to another DP83867 chips so they can convert both SGMII traffic directions to MDI (this means that monitoring PHYs would be unidirectional, only RX would be connected)?

Thanks

  • 0
    TI__Expert 7040 points

    Hi Luka,

    Yes, you can use the DP83867E in a back-to-back SGMII configuration to achieve the setup you've described. You can also set the DP83867 SGMII interface to a forced speed to bypass the auto-negotiation process. 

    Can you please share a block diagram of the PHY to LVDS-Buffer to PHY you are describing?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 50 points

    Hi Justin,

    thanks for the confirmation, will forcing the SGMII interface to a fixed speed maybe cause problems for MDI auto-negotiation? I read in the datasheet that it shouldn't be a problem because you can force it to MDI resolved speed, but I want to be sure.

    Here is the block diagram of the whole system, NB6N11S ( https://www.onsemi.com/pub/Collateral/NB6N11S-D.PDF ) is a 2.5Gbit 1:2 LVDS fanout buffer from ONsemi (sorry for the orientation, for some reason it won't rotate properly).

    Regards,

    Luka

  • 0 in reply to Luka Kosanovic
    TI__Expert 7040 points

    Hi Luka,

    You will be able to force SGMII to disable auto-negotiation and the speed will be dictated by the cable side of the PHY. In this configuration you will need to be able to control each PHY to ensure all are configured to the same speed. 

    In SGMII forced mode, I don't see an issue with the fanout to the monitoring PHYs and the DP83867 will act to forward the SGMII RX data to the cable.

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 50 points

    Hi Justin,

    Of course every PHY will be controlled through SMI bus, you confirmed everything that I needed to know. Thank you for your help.

    Regards,

    Luka