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DS90UB954-Q1: DS90UB954-Q1

Goran Fiolic
Intellectual 420 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UB933-Q1,

I am using DS90UB954-Q1 paired with DS90UB933-Q1. I am constantly getting "Packet buffer error" (RX_PORT_STS2 register). I run BIST using pixel clock from image sensor connected to DS90UB933-Q1 and I did not get any errors (I run test for several hours). CSI lane speed is set to 1.6Gbps and all 4 lanes are used. I am using RAW10 mode. I tried to modify CSI registers 0x44-0x48 but that did not help. Besides input being faster than the output (which is not the case here), what else may be causing this "Packet buffer error"?

  • 0
    TI__Intellectual 1025 points

    Hello Goran,

    Unless your data transmission rate is 400 Mbps, you should not change any CSI timing registers. The defaults are compliant with MIPI recommendations. What are your video parameters (frame rate, resolution, etc.)?

    Please send me the values in CSI_PLL_CTL (0x1F), FWD_CTL1 (0x20), FWD_CTL2 ( 0x21), CSI_CTL (0x33), and CSI_CTL2 (0x34)  so I can review your configuration.

    Regards,

    Carrie  

  • 0 in reply to Carrie Kemmet
    Intellectual 420 points

    Hi Carrie,

    I am using video with the following parameters:

    Resoluiton - 1280x720, Frame rate - 30FPS, Video format - 8bit YUV, Video Clock frequency - 96MHz.

    Registers:

    0x1F - 0x00

    0x20 - 0x00

    0x21 - 0x01

    0x33 - 0x03

    0x34 - 0x40

    Regards

    Goran

  • 0 in reply to Goran Fiolic
    TI__Intellectual 1025 points

    Hello Goran,

    Check that register 0x6D is configured for RAW10 mode, and that the RAW10 mode setup in PORT_CONFIG2 is correct. Also verify that the RAW10 VC-ID for each port is different.

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    Intellectual 420 points

    Hi Carrie,

    While I was on vacation, my colleague managed to find what was actually wrong. The problem was not related to register setup, but to 25MHz reference clock bad signal integrity. Upon improving signal integrity, the problem was gone, so we consider this case closed.

    Best Regards

    Goran