Hi,
I am using an updated custom board that uses the TVP5147M1 to receive both NTSC and PAL and send the decoded parallel video bus to a FPGA and this interface is working fine. The previous revision of this board designed by somebody else also has the TVP5147M1 and is able to receive a third video format that has a 103.125MHz pixel clock. The datasheet indicates a typical DATACLK high and low time of 18.5ns but does not mention a minimum and I don't have enough details about the PLL being used to determine if the TVP5147M1 is able to support that high of a pixel clock. Can you please let me know if this part can support pixel clock frequencies this high and some more details about the internal PLL being used to generate DATACLK? Frequency range, resolution, dividers, etc.?
Thank you.
