Hello TI team,
We are using a few I2C buffer parts PCA9515A in our design. Ironic enough the buffer on 2 of the boards out of 10 has gotten damaged. The I2C_CLK pin of master side is the one getting damaged. We measure a resistance of 100 to 200 ohms between the clk pin: 2 and GND pin: 4).
I know this is quite odd, both clk and data are open drain driven, therefore I can't think a possibility of any data contention issue. The bus is a single master bus, therefore FPGA is the only master and driver of the clock. The low level on both CLK and Data are close to 0.2V on the master side . The output of the buffer low level is at 0.5V as advertised in the data sheet.
Have you heard of this issue in the past? Could there be a glitch during power up that is confusing the clock driver? The enable is tied to 3.3V and NOT the POR reset, therefore there can be a possibility of glitch during powerup, <will be tested.>
The pullup on the master side is 2.2K to 3.3V. (less than 1.5mA sink current)
Thanks,
Bahram
