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PCA9515A: CLK pin 2 measures 100 ohms to GND

Part Number: PCA9515A


Hello TI team,

We are using a few I2C buffer parts PCA9515A in our design. Ironic enough the buffer on 2 of the boards out of 10 has gotten damaged. The I2C_CLK pin of master side is the one getting damaged. We measure a resistance of  100 to 200 ohms between the clk pin: 2 and GND pin: 4).

I know this is quite odd, both clk and data are open drain driven, therefore I can't think a possibility of any data contention issue. The bus is a single master bus, therefore FPGA is the only master and driver of the clock. The low level on both CLK and Data are close to 0.2V on the master side . The output of the buffer low level is at 0.5V as advertised in the data sheet. 

Have you heard of this issue in the past? Could there be a glitch during power up that is confusing the clock driver?  The enable is tied to 3.3V and NOT the POR reset, therefore there can be a possibility of glitch during powerup, <will be tested.>

The pullup on the master side is 2.2K to 3.3V. (less than 1.5mA sink current)

Thanks,

Bahram 

  • Hey Bahram,

    Do you have scopeshots of the working devices on the side that the SCL pin was damaged? (zoom in close to a falling wave and set resolution/sampling HIGH)

    Are you communicating on board or is there communication through a cable?

    My initial guess is the device may be seeing undershoots due to parasitic inductance which is going past our absolute min values and damaging the device. (Usually more common in cable transmission though I have seen it happen onboard once).

    -Bobby

  • Hi Bobby,

    I actually thought the same thing, that the undershoot is either killing the ESD diode from GND to the pin or as you said damaging the part. Looking at the signal there is no undershoot whatsoever. The fall time is 9nsec on <10" of trace. 

    There is a possibility that the I2C beagle inspector with 12" ribbon is doing the damage <to be tested>

    The power on is clean with 1msec sofstart. 

    To be continued >>>

    thanks,

    Bahram

  • Hi Bahram,

    Do you have any I2C switches/level translators on the I2C bus? That waveform looks like an affect/byproduct from a pass FET holding the voltage at a step for single digit nanoseconds time due to differences in loading on both sides. The step will be at about Vcc-Vth for the pass FET. Changing the drive strength (12mA to 6mA for example) should slightly narrow the width of this but it shouldn't be causing damage to the device.

    Are you able to increase the resolution and sampling on that falling edge? I'm wondering if we are catching the full negative undershooting or if we are still undersampling it.

    "There is a possibility that the I2C beagle inspector with 12" ribbon is doing the damage"

    I have seen something like this cause some minor undershooting though 12" likely isn't enough to damage something.

    -Bobby