SN65HVD1786: Any issue to add capacitors between A/B line and GND.

Max-san,

Thank you for your kindly support.

I'm original requester to Hattori-san about this question.

Are there any concern about adding load capacitor other than slow down the signal transitions?

I'm worried about output current increase momentaly by charge/discharge these load capacitor.

Is it OK that Io exceeds your recommended value 60mA momentaly?

Best regards,

Yamada

Hello Yamada-san,

Yes, the 60 mA recommended maximum is not a firm limit and is just specified in order to provide a reference point for DC loading under normal conditions (e.g., to help guide termination resistance selection).  The device should not become damaged due to high output current - it is designed to handle short-circuit conditions where the current could be as high as 250 mA (internally limited).

However, it is good to recognize that the driver output current will be higher on signal transitions due to the charging/discharging of the capacitance.  This will increase the power dissipation in the transceiver, resulting in a hotter internal temperature.  A method for calculating the power dissipation due to AC loading is described in this blog:

https://e2e.ti.com/blogs_/b/analogwire/archive/2018/06/14/how-to-calculate-the-power-dissipation-of-high-speed-rs-485-transceivers

The capacitive loading should also inform the VCC decoupling capacitance selection, since this capacitance would need to provide the switching current in cases where the driver transition time is faster than the load transient response of the external VCC regulator.  100 nF is a common value, but if external loading is a similar order of magnitude then a higher value like 1 uF or 10 uF could be used to minimize voltage sag.

Regards,
Max

Hellow Max-san,

Thank you very much for your kindly answer.
I will take care of internal heat generation and decoupling capacitance selection.

Could you please how to design the termination resistance and resistive voltage divider?
Can I design by referensing 2.4.1.6 in TIDA-010035?

Hello,

Yes, you could reference that figure. For a more detailed description, you could reference this application note:

Note that this document modifies the calculations somewhat so that the total equivalent differential impedance of the failsafe termination network matches the characteristic impedance of the transmission line (for example, 120 Ohms).  This allows for better impedance matching, improving signal integrity by reducing the amplitude of reflections that can occur at the end of the line.

The reference design that you mentioned demonstrates a method of combining DC power and RS-485 signaling onto a common differential pair.  In case your application is similar, I would recommend considered our newer THVD8000 device.  It is based on RS-485 transceiver design but implements on-off- keying modulation and demodulation at a configurable carrier frequency to better support AC-coupling coupling of lower-speed (<1 Mbps) RS-485 data in order to more easily combine with power lines.

Please let me know if you have any further questions.

Regards,
Max

Hi Max-san,

Thank you for your answers and introducing your recommendation parts.
 I will verify our problems based on your anwers.
If I have more questions, I will contact you again.
Thank you so much for your kindly suports.

Regards,

Yamada