• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 665 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB954-Q1: TI954 and TI953 case

pradeep TG
Prodigy 240 points
Part Number: DS90UB954-Q1

Hi Team,

We are using DS90UB954-Q1 and DS90UB953 SERDES for AR0144AT camera below is the flow

host-->TI954-->FPD-->TI953-->AR0144AT 

port used for camera is CSI_CLK0 

we need to reset the AE0144AT from HOST, TI953 GPIO_2 is connected to reset of AR0144AT how we can achieve this from HOST below are the I2C 7 bit address

TI954 ---> 0x38 

TI953 ---> 0x30

  • 0
    TI__Mastermind 30515 points

    Hi, 

    what is the meaning of CSI_CLK0? how to use it?

    for your issue, you can use two methods:

    1. you can Set the reg. GPIO2 output high or low directly

    2. you can use the GPIO pass-through control from 954's GPIO, for this method, you need map remote GPIO control from 954. in d/s, it has remote GPIO control example.

    regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 240 points

    Hi Steven,

    Thank you for the response 

    port 0 we are using for input from serializer.

    We can GPIO pass-through control, Can we control 953 gpio from processor GPIO, if we enable remote GPIO 

  • 0 in reply to pradeep TG
    TI__Mastermind 30515 points

    Hi TG,

    sure, you can use processor's GPIO to control UB953's GPIO ouput status, please check ub954 d/s in section 7.4.13 on GPIO feature. meanwhile you need set the mapped GPIO pin in 953 side as remote output feature.

    7.4.13.4 Back Channel GPIO Each DS90UB954-Q1 GPIO pin defaults to input mode at start-up. The deserializer can link GPIO pin input data on up to four available slots to send on the back channel per each remote serializer connection. Any of the seven GPIO pin data can be mapped to send over the available back channel slots for each FPD-Link III Rx port. The same GPIO on the deserializer pin can be mapped to multiple back channel GPIO signals. For each 50-Mbps back channel operation, the frame period is 600 ns (30 bits × 20 ns/bit). For 2.5-Mbps back channel operation, the frame period is 12 µs (30 bits × 400 ns/bit). As the back channel GPIOs are sampled and sent each back channel frame by the DS90UB954-Q1 deserializer, the latency and jitter timing are each on the order of one back channel frame. The back channel GPIO is effectively sampled at a rate of 1/30 of the back channel rate or 1.67 MHz at fBC = 50 Mbps. TI recommends that the input to back channel GPIO switching frequency is < 1/4 of the sampling rate or 416 kHz at fBC = 50 Mbps. For example, when operating in 4-Gbps synchronous mode with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the data rate when linked over the back channel is shown in Table 10. Table 10. Back Channel GPIO Typical Timing BACK CHANNEL RATE (Mbps) SAMPLING FREQUENCY (kHz) MAXIMUM RECOMMENDED BACK CHANNEL GPIO FREQUENCY (kHz) TYPICAL LATENCY (us) TYPICAL JITTER (us) 50 1670 416 1.5 0.7 10 334 83.5 3.2 3 2.5 83.5 20 12.2 12 In addition to sending GPIO from pins, an internally generated FrameSync or external FrameSync input signal may be mapped to any of the back channel GPIOs for synchronization of multiple sensors with extremely low skew. (see FrameSync Operation). For each port, GPIO control is available through the BC_GPIO_CTL0 register 0x6E (see Table 120) and BC_GPIO_CTL1 register 0x6F (see Table 121).

    regards,

    Steven