PCA9306: PCA9306 parameter

Hello,

The datasheet spec's the timing parameter tPLH in a weird way. The set up involves forcing a reference voltage on the enable pin that is equal to the ViH level. The reason why I say this is weird is because, in almost all application uses for this device, the enable pin's voltage is Vref1+(~0.6V). When you force the enable voltage to be set to your ViH, you are effectively forcing the device to always be in the linear region. This will give faster prop delay times since you are always conducting the pass FET. In typical applications, you would switch between cut off and linear which adds ~100ns of prop delay time depending on the voltage and how you reference/define prop delay.

"So I'd like to ask you something that  whether  the rise time of the input signal must be less than 2ns in order to meet the target."

You don't need to try to force the rise time to meet these parameter numbers, they are there just for reference. The device will work even if your prop delays are in the 100ns range. In most I2C applications (100khz and 400khz), a 100ns prop delay isn't going to affect signal integrity/timing.

-Bobby