DP83848C: Can't ping enet phy chip

Hi George,

Can you please confirm the clock and the magnetics meet the requirements on the DP83848? 

I am also curious as to what the clock signals look like on the good and bad board to see if there is a signal integrity issue.

Auto-mdix is used to determine whether the device requires a straight or crossover cable. The switching leads me to believe there is some instability on the board

Thanks,

Cecilia

I looked at the clock and it looks like the clock on a working board.  I replaced the crystal with a 25Mhz oscillator and I get the same results that I can't ping.  I also tried strapping the MDIX enable signal to ground with a 2.2K ohm resistor and could verify that it was disabled by reading the Phy control register and bit 15 was off.  When I do this, the MDIX bit doesn't change like I saw before, but I still can't ping the chip.  The magnetics look like figure 7.2 in the datasheet.

I have the values of the registers after the ping fails on a bad board.  Could you take a look to see if there's something obviously wrong?  I'm trying to run in 100Mbps, full duplex mode.  I'd appreciate it and any other suggestions as well.  Thanks.

00 - 0x1000

01 - 0x7869

02 - 0x2000

03 - 0x5C90

04 - 0x0181

05 - 0xCDE1;  The datasheet shows a second page for this register.  I don't have it shown.  How do I read it? 

06 - 0x000F

07 - 0x2801

16 - 0x0615;  This is the register that intermittently changes to 0x4615 if I don't have MDIX disabled.

17 - 0x0000

18 - 0x2C00

19 - 0x0000

20 - 0x0000

21 - 0x0000

22 - 0x0100

23 - 0x0001

24 - 0x0000

25 - 0x8020

26 - 0x0804

27 - 0x0000

29 - 0x6011

Hi George,

Thanks for sharing the registers. It looks like reg 0x1 is reading 7869 which signifies that there is no link. Could you read that register twice just to confirm since it is a latch low pin? 

If the case is that there is no link then the issue is on the MDI side. Can you confirm you are seeing the FLP signals on the lines? 

Thank you.  Does MDI side mean the TD+/- RD+/- or the TXD(3:0) and RXD(3:0)?

I found the answer to my previous question so you can ignore it. 

I have another question.  I have pin 42 (COL/PHY AD0) pulled low through a 2.2K resistor so the phy address is zero and the chip comes up in isolate mode.  Can the chip be removed from isolation just by writing to the basic control register after power up or do I have to do something with the phy address?  I'd like the phy address to stay zero and be out of isolation.

Also, what is this mode used for?

Hi George,

Yes, you can configure the PHY out of isolate mode using register 0x00 bit 10 

MII Isolate mode is used for debugging purposes as it prevents the PHY from transmitting packets to the MAC while still creating a link.