This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IR: DP83867IRREG loopback setting at 100Mbps

Part Number: DP83867IR

Hi,

We are working on the DP83867 PHY chip loopback configuration.

To run at 100Mbps we have set the 0x0009 ( 1000Base-T Configuration Register- CFG1) to value - 0x0000.

Connected RJ45 Cable to PC and we are able to detect Link up status at 100Mbps.

For External Loopback :

We are doing the below setting to check the External loopback but we are not getting any output on the Rx lines. ( no bit change observe) 

We are getting LOOPCR register value as 2 but according to datasheet this value should be 0xE720.

If we set this register then all other register value becomes 0. So we are not modifying this register value.  

Steps Followed :

1) Connected Ethernet loopback cable ( Shorted TX lines to RX Lines)

2) Write register 0x001F to 0x8000 to apply a software reset.
3) Write register 0x0000 to 0x2100 to disable Autonegotiation, 100Mbps and Full duplex.
4) Write register 0x0032 to 0x00D3 to enable RGMII: === NOTE: This requires REGCR/ADDAR access (extended register space)
   a) Write register 0x000D to 0x001F to prepare to load RegAdd 32 into ADDAR
   b) Write register 0x000E to 0x0032 to point to RegAdd 32
   c) Write register 0x000D to 0x401F to prepare to load data for RegAdd 32 into ADDAR
   d) Write register 0x000E to 0x00D3 to enable RGMII
5) Write register 0x0016 to 0x0010 to enable External loopback.
6) Write register 0x001F to 0x4000 to apply a software restart.
7) Transmitting data on the RGMII  TX lines

No data received on the RX lines.

For Digital Loopback :

We are doing the below setting to check the Digital loopback but we are not getting any output on the Rx lines. ( no bit change observe) 

We are getting LOOPCR register value as 2 but according to datasheet this value should be 0xE720.

If we set this register then all other register value becomes 0. So we are not modifying this register value.  

Steps Followed :

1)  Removed the RJ45 Connection to PC

2) Write register 0x001F to 0x8000 to apply a software reset.

3) Write register 0x0000 to 0x2100 to disable Autonegotiation, 100Mbps and Full duplex.
4) Write register 0x0032 to 0x00D3 to enable RGMII: === NOTE: This requires REGCR/ADDAR access (extended register space)
   a) Write register 0x000D to 0x001F to prepare to load RegAdd 32 into ADDAR
   b) Write register 0x000E to 0x0032 to point to RegAdd 32
   c) Write register 0x000D to 0x401F to prepare to load data for RegAdd 32 into ADDAR
   d) Write register 0x000E to 0x00D3 to enable RGMII
5) Write register 0x0016 to 0x0004 to
   - enable digital loopback.
6) Write register 0x001F to 0x4000 to apply a software restart.
7) Transmitting data on the RGMII  TX lines

No data received on the RX lines.

Are we missing something?

Does LOOPCR register need to be set to 0xE720 value? (After setting it to 0xE720 we are getting other register value also as zero) 

If YES, please mention the sequence in the above steps.

Waiting for your Reply,

Vipul

  • Hi Vipul,

    We have our DP83867 troubleshooting application note that goes over the different loopback modes. 

    https://www.ti.com/lit/an/snla246a/snla246a.pdf

    Please review and let me know if you still are seeing issues.

    Thanks,

    Cecilia

  • Hi Cecilia,

    We have gone through the above document but still we are not getting loop back test output.

    Steps Followed :

    1) Write register 0x001F to 0x8000 to apply a software reset.

    2) Write register 0x0000 to 0x2100 to disable Autonegotiation, 100Mbps and Full duplex.

    3) Write register 0x0032 to 0x00D3 to enable RGMII

    4) Write register 0x0016 to 0x0004 to enable digital loopback.

    5) Write register 0x001F to 0x4000 to apply a software restart.

    6) Transmitting data on the RGMII  TX lines

    As per the data sheet LOOPCR register 0x001F need to be set to value 0xE720 value. 

    Default value for this register is 0xE721 but we getting this value as 0x0002. 

    Now as soon as we set this register to 0xE720 we are not able to configure all other register provided in the steps above.

    Even after configuring those register they will be read as 0 only.

    Can you please confirm the role of 0x00FE ( LOOPCR ) register in the Loopback mode configuration.

    If yes please mention the sequence for configuring all the registers. 

    Please reply as soon as possible,

    Thanks,

    Vipul

  • Hi Vipul,

    Have you tried confirming the more shallow loopbacks have worked too? such as MII loopback or PCS loopback? 

    This register is a design specific configuration so I do not have the exact details as to the role however it is used specifically for loopback configuration. 

    Please try the sequence you tested in your comment but without this register change and please try PCS or MII loopback. 

    Can you also confirm your crystal or clock on the XI is stable and within the specs of our datasheet?

    Thanks,

    Cecilia

  • Hi Cecilia,

    We have even tried the MII loopback but still LOOPBACK test is not working

    Steps Followed :

    1) Write register 0x001F to 0x8000 to apply a software reset.

    2) Write register 0x0000 to 0x2100 to disable Autonegotiation, 100Mbps and Full duplex.

    3) Write register 0x0032 to 0x00D3 to enable RGMII

    4) Write register 0x0000 to 0x6100 to enable digital loopback.

    5) Write register 0x001F to 0x4000 to apply a software restart.

    6) Transmitting data on the RGMII  TX lines

    After doing above steps we are still not able to see any bit change on the RX lines.

    Note : Crystal clock is stable and hardware is tested with functional code.

    In one of the E2E Forum comment it was mention like Loopback got worked after writing the LOOPCR register.

    Please check the link below:

    https://e2e.ti.com/support/interface/f/138/t/684210

    We have even tried writing the LOOPCR register to value 0xE720 but after that all other register will get reset to 0 only.

    Let me know your thoughts on the same.

    Thanks,

    Vipul

  • Hi Vipul this looks to be the same question as you submitted today. Please close this thread and continue in the other E2E post.

    Thanks,

    Cecilia

  • Hi Ti Team,

    My issue is not resolved. Resolution provided by your team member is not satisfactory. 

    We are working on the Loopback testing but it is not working with DP83867 chip.

    Our hardware is tested properly with Functional code and there is no issue with the hardware schematic as we are using the EVAL board only. 

    We have tried External, Digital and MII loopback as well but we are not getting any output.

    Please check the earlier reply to know the steps which we have followed and correct us if we are missing anything.

    Thanks,

    Vipul 

  • Hi Vipul,

    Can you please share the register dump for when you write and read back the registers you are configuring?

    I will reach out to our internal team to confirm if this is needed and why you are seeing the 0s after writing to reg 0xFE

    The steps for your configuration look correct I will need to confirm with our team if there is anything else missing.

    Thank you for your patience,

    Cecilia