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TI UB964 deserilizer MIPI CSI ERROR checksum error/header ecc error

Qingcai Tang
Prodigy 130 points

Hello .

I am developing a serializer- deserializer project.

And my hardware environment is

host MCU: IMX6QP

deserializer:UB964

serializer:UB933

when i opened my v4l2 device and configured mipi csi , the  i.mx6 mipi csi log shows below :
mipi csi2 error1 mipi_reg 0x11000000!
mipi csi2 error2 mipi_reg 0x100!

mipi csi2 error register descriptions as:

CSI ERROR1

Bit28.
err_ecc_double
Header ECC contains 2 errors. Unrecoverable.
Default Value: 0
Bit24.
vc0_err_crc
Checksum Error detected on Virtual Channel 0
Default Value: 0

CSI ERROR2

Bit8.
vc0_err_ecc
corrected
Header error detected and corrected on Virtual Channel 0
Default Value: 0

But  i read  UB964 registers,it shows below :

UB964_read_reg:addr 0x30 reg 0x7a=0x0
UB964_read_reg:addr 0x30 reg 0x4e=0x4
UB964_read_reg:addr 0x30 reg 0x4d=0x3


UB964_read_reg:addr 0x30 reg 0x73=0x3
UB964_read_reg:addr 0x30 reg 0x74=0xc0
UB964_read_reg:addr 0x30 reg 0x75=0xa
UB964_read_reg:addr 0x30 reg 0x76=0x0

In my opinion ,0x7a = 0 it means no errors about csi ,right ?

0x73~0x76 shows that deserilizer has received image data 1280x960;

How about this issue ?

why does i.MX6 show the mipi csi error1/error2 ?

Best regards.

  • 0
    TI__Intellectual 1025 points

    Hello,

    Have you tried using the pattern generator feature on the 964?  By enabling the pattern generator output to the port that you are using, you can see if the error is occurring between the deserializer and i.MX6. Try to send a pattern from the deserializer to the iMX6 and let me know whether the same errors occur in that case or not. 

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    Prodigy 130 points

    Hi Carrie:

    I have not tried using the pattern generator feature on UB964 and I am a rookie.

    I got "8.5.6.1 Code Example for Pattern Generator" in DS90UB964 datasheet and i will test this sample code in my hardware environment.

    Does this sample code could generate a CSI2 pattern with 1280x720P30+ VC0+YUV422 ?

    If not ,could you tell me how to generate a CSI2 pattern with 1280x720P30+ VC0+YUV422.

    Thanks for your reply.

    Best wishes.

    Qingcai

  • 0 in reply to Carrie Kemmet
    Prodigy 130 points

    Hi Carrie:

    I have tried using the pattern generator sample code by "8.5.6.1 Code Example for Pattern Generator" in DS90UB964 datasheet.

    It seems no mipi csi errors report .

    My workflow is

    1 INITIAL UB964 by "8.5.6.1 Code Example for Pattern Generator"

    2 STREAM OFF OUTPUT by writing ub964 0x33=0x00;

    3 CONFIGURE IMX6 MIPI CSI2,like mipi_csi2_reset(),set_datatype() and so on .

    4 STREAM ON OUTPUT by writing ub964 0x33=0x01.

    5 READ MIPI CSI2 STATUS by reading imx6 host register .

    There are not errors report in the end ,error1 = 0  and error2 = 0 .

    So i think the hardware environment is OK  ,right ?

  • 0 in reply to Qingcai Tang
    TI__Intellectual 1025 points

    Hello Qingcai,

    Thank you for running the pattern generator. These results indicate that the errors are likely occurring somewhere before the deserializer. All of my suggestions below are for deserializer configuration and will help you identify the problem or filter it out.

    Please verify that the back channel frequency of the 964 is set to 2.5 Mbps (bits 2:0 to 0b000). Note that 0x58 is a port specific register, so the port select register (0x4C) has to be configured for the right RX port. Also once the errors have been detected, please send me the values of the RX port status register (0x4D and 0x4E) for that port.

    Additionally, you can try configuring register 0x7D, port pass control. This register determines the conditions that will cause the packet to be discarded. By enabling packet discard on different errors, the deserializer could filter out the error before it reaches your SoC.

    Finally, make sure that the port mode in register 0x6D is configured correctly. You can try discarding the first packet if it’s truncated in RAW mode (enable bit 3). Note that only RAW12 LF mode (0x6D[1:0] = 0b01) and RAW10 mode (0x6D[1:0] = 0b11 are 933 compatible.

    Regards,

    Carrie

  • 0 in reply to Carrie Kemmet
    Prodigy 130 points

    Hi Carrie:
    I have solved my problems by reading IMX6 documents.

    Thanks for your support.

    Best Regards

    Qingcai