Other Parts Discussed in Thread: DP83869
Hi team,
My customer is using DP83869 fiber mode and use FPGA to provide DP83869 XI clk.
They want to have RX_CLK synchronous to TX_clk(100Mbps, MII and RGMII are both OK), but RX_clk seems only synchronous with link partner XI clk.
However, they used DP83848 before, and both RX data and TX data of DP83848 can be synchronous with XI clk in MII mode. This kind of same clk domain data help FPGA code development more easier.
Can you help check if there is any method to sync DP83869 RX_clk with TX_clk? In other words make RX data and TX data in same clk domain?
Thank you
Yunjing
