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SN65LVDM050QDQ1 - Measured channel-to-channel skew on reception ~1ns instead of <200ps at 200Mbps

ETTORI Marc
Prodigy 30 points
Other Parts Discussed in Thread: SN65LVDM050

Related Case No.: CS0253265

Dear TI support,

On our board, we are SN65LVDM050QDQ1 part to provide communication protocol (clock + data) between two FPGA devices.
The clock operates at 100MHz (e.g. 200Mbps), while the data is generated on each rising edge of the clock (so 100Mbps).

The SN65LVDM050QDQ1 we are using indicates:
- Support up to 500Mbps,
- Typical channel-to-channel skew 0.2ns

But our measurements shown that: the SN65LVDM050QDQ1 component induces a channel-to-channel skew of around 1ns (at least) between the two channels (clock and data) from the LVDS side to the Single-Ended side (reception).

As we noticed that on the SN65LVDM050 part, the reception side can be run up to 100Mbps, we are wondering whether this is not also the case for the SN65LVDM050QDQ1 part so that the channel-to-channel skew cannot be according to the datasheet when using a 100Mhz clock.

Please could you confirm that for SN65LVDM050QDQ1, the channel-to-channel skew is @0.2ns in both transmition and reception?

PS: In attached picture, there are the measurements we made. On top this is clock and data (LVDS side), while below this is clock and data (single-ended side).

Thank you very much in advance,
BR,

Marc Ettori

  • 0
    TI__Mastermind 35130 points

    Hi Marc,

    But our measurements shown that: the SN65LVDM050QDQ1 component induces a channel-to-channel skew of around 1ns (at least) between the two channels (clock and data) from the LVDS side to the Single-Ended side (reception).

    From the bolded section above, it seems you are measuring propagation delay? You didn't attach any pictures.

    In any case, the datasheet does not specify a maximum channel-to-channel skew - it only gives a typical value over the entire recommended operating conditions of the device.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 30 points

    Hi again,

    We found the issue, as related to the description within the SN65LVDM050QDQ1 datasheet.

    The issue comes from the fact that we run the interface at 200Mbps, as the datasheet (Q1 version) specifies max. 500Mbps. Then our understanding was that the selected speed was correct for this component.

    However, the SN65LVDM050QD datasheet indicated max. speed of 100Mbps for the not Q1 version. We run the interface at 100Mbps (we are using the Q1 version), and the channel to channel skew was considerably affected in the sense that under these conditions the signals were clean and accordingly to the datasheet (at 200Mbps it was considerably impacted with the delay that was indicated.. we may have run the interface out of the component specifications).

    The information that is lacking on the current SN65LVDM050QDQ1 datasheet is the speed limitation on the reception side (LVDS to single-ended), as it is indicated within the not-Q1 version of the component's datasheet.

    Regards,

    Marc