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DS90UB954-Q1: Frame level error for VC0 and CRC error with using the pattern generator of ds90ub954-q1

xinxin wang1
Prodigy 80 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: ALP

I have tried the pattern generator of ds90ub954-q1. The xilinx FPGA mipi csi-2 rx ip core is used to analyze the mipi signal from DS90UB954-Q1.  I can read video data from mipi csi-2 rx ip core. But there are error status: Frame level error for VC0(Asserted after an FE when the data payload received between FS and FE contains errors.),CRC error(Asserted when the computed CRC code is different from the received CRC code). 

Could you give me some advice? 

Best Regards!

  • 0
    TI__Mastermind 30515 points

    Hi,

    what is the application in your project? 

    for your issue, please check

    1. if the patgen. is correct or not?

    2. pls check the link between 954 output and FPGA's input is good design or not?

    regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 80 points

    Hi,

    The application is: I used xilinx FPGA mipi csi-2 rx ip core to receive the mipi signal from DS90UB954-Q1. 

    1. if the patgen. is correct or not?

    How to check it?

    2. pls check the link between 954 output and FPGA's input is good design or not?

    How to check this?

    This error can be cleared and the output data of  mipi csi-2 rx ip  core is correct.

    Best Regards!

  • 0 in reply to xinxin wang1
    TI__Mastermind 30515 points

    1. you can use TI's ALP tool to enable 954 internal pattern gen., and check if your CSI2 sink can work well?

    2. this is dependent on your FPGA internal CSI2 core. for our 953, it has CSI2/DPHY error detection registers, so you can check if it has issue or not here inside your CSI2 sink.

    basically, you need identify this issue is from the link between sensor and 953, or between 953 and 954, or between 954 and your CSI2 sink.

    regarsd,

    Steven