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DP83822I: RESET_N sometimes leaves PHY stuck

M.A.M
Expert 8805 points
Part Number: DP83822I

Hi,

My customer reports a situation that I cannot explain. Please help.

"We have found that the Ethernet PHY (DP83822) does not always come correctly out of reset.

When we boot the product I do not believe we have seen any issue. The issue comes when we reboot our host processor, this then generate a reset pulse to the PHY and sometimes the PHY does not come up correctly after this.

Attached are captures of RESET_N and RX_CLK. I have just driven RESET_N low, then high from our host and here you can see that once in a while PHY does not start correctly. We are not cycling anything other such as power etc. – only RESET_N pin.

I first expected it might be due to actual low level of the RESET_N signal (on measurements 310mV – we are using diode to pull low) however I also tried reducing this further to 10mV and no change.

I will try to increase risetime, but other then that I am a little perplexed on what is causing this.

For reference we are currently running: AVD = 3.3V, VDDIO = 1.8V.

Also tried using phytool to read out some registers (0x00 and 0x17) and when in this mode they both readback 0xffff."

Not OK operation:

OK operation:

Looking forward to your advice.

B.r M.A.M

  • 0
    TI__Genius 9920 points

    Hi M.A.M.

    Does the processor also reset the clock? Are you using a crystal as the input of your XI pin? XI clock must be stable for 10us during the RST pulse width. 

    Also I don't think I see the measurements on the scope but what are the RST pulse widths on the Not OK and OK operations?

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    TI__Expert 8805 points

    Cecilia,

    Customer answers  "We are using external crystal connected directly to the PHY. And it appear there is no stop of oscillation during reset."

    The scope show that RESET_N is low for a 18ms pulse when NOK, and 13ms when OK.

    I hope it clarifies.

    B.r  M.A.M