TPS65987D: Load Capacitance

Garret Holt

Part Number: TPS65987D
Other Parts Discussed in Thread: TPS65987

Hi Team,

We are working with TPS65987 and have a question regarding the allowable load capacitance. In the datasheet, table 27 on page 54 specifies an absolute max of 120uF capacitance on a PowerPath used as a sink. Is this a limitation of the TPS65987 itself, or a limitation imposed by USB-C specifications? I noticed that even the dev board has at least ~350uF of capacitance on whichever of the power paths is connected to SYS_PWR (dev board schematic page 12, "Fast Role Swap caps" plus others) -- and the dev board works fine. In the design we have greater than 120uF and do not want to run into issues.

Thank you!

Garret

over 5 years ago

0 Hari Patel1 over 5 years ago

TI__Genius 12700 points

Hi Garrett,

I believe you should be fine with that. How much capacitance do you have in the design currently? I can double check with the team and get back to you.

Thank you,

Hari

0 Garret Holt over 5 years ago in reply to Hari Patel1

TI__Intellectual 1050 points

Thanks Hari, nearly 1000uF currently.

Regards,

Garret

0 Hari Patel1 over 5 years ago in reply to Garret Holt

TI__Genius 12700 points

Hi Garrett,

I've talked to the team and the customer should be fine with this capacitance. The only concern would be if there is a large amount of capacitance, the in rush current paired with soft starting the FETs could potentially stress the device.

Thank you,

Hari

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TPS65987D: Load Capacitance