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TLK2711-SP: Feeding clock to tlk2711-sp

chunjie wang
Intellectual 270 points
Part Number: TLK2711-SP

Dear,

I'm making the hardware design of TLK2711-SP in combination with FPGA. For the clock, I have a doubt that how to feed the reference clock to TLK2711 and FPGA.

According to the spec requirement, the peak-peak jitter of the reference clock should be less than 40-ps. In order to meet the demand, it's a better method of using OSC to feed the clock to the TLK2711. The diagram is shown as follows.

As known, we get two clocks from the fanout chip, name that tx_clk, and ref_clk. The ref_clk will be used to send the 16-bit data from FPGA to TLK2711. Under such a circumstance, the phase between tx_clk and data cannot be kept aligning, and this will affect the data captured by TLK2711? Can TLK2711  handle the phase difference between the clock and data internally?

Thanks

Chunjie

  • 0 in reply to chunjie wang
    TI__Mastermind 19235 points

    Hi,

    Refer to the datasheet for timing limits applicable to TXCLK. a hold time of 0.4ns is listed for TXD relative to TXCLK. See datasheet snapshot below.

    7.5 TTL Input Electrical Characteristics

    over recommended operating conditions (unless otherwise noted),

    TTL signals: TXD0–TXD15, TXCLK, LOOPEN, LCKREFN, ENABLE, PRBS_EN, TKLSB, TKMSB, PRE

    PARAMETER

    TEST CONDITIONS

    MIN TYP MAX

    UNIT

    VIH High-level input voltage

    See Figure 1

    1.7

    V

    VIL Low-level input voltage

    See Figure 1

    0.8

    V

    IIH Input high current

    VDD = MAX, VIN = 2 V

    40

    µA

    IIL Input low current

    VDD = MAX, VIN = 0.4 V

    –40

    µA

    CI Receiver input capacitance

    6

    pF

    tr Rise time, TXCLK, TKMSB, TKLSB, TXD0 to TXD15

    0.7 to 1.9 V, C = 5 pF, See Figure 1

    1

    ns

    tf Fall time, TXCLK, TKMSB, TKLSB, TXD0 to TXD15

    1.9 to 0.7 V, C = 5 pF, See Figure 1

    1

    ns

    tsu TXD0 to TXD15, TKMSB, TKLSB setup to ↑ TXCLK

    See Figure 1 (1)

    1.5

    ns

    th TXD, TKMSB, TKLSB hold to ↑ TXCLKS

    See Figure 1 (1)

    0.4

    ns

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer