TLK1501EVM: TLK1501EVM

Request noted. I will target to provide my inputs by close of business tomorrow (Tuesday).

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hi,

Can you confirm the following:

• That proper jumper placement is used for J5?
  • Per the user's guide: The TX and RX parallel connectors, J1–J4 of Figures 8 and 10 in Appendix A, provide a connection for both transmitted and received data. The reference clock is supplied through SMA connector J8 and jumper J5 must be installed between pins 1 and 2
• That PRBSEN is pulled high on your board?
  
  • On the EVM board R11 must have a 4.7kohm on it, which then pulls PRBSEN to VDD

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hello Rodrigo,

Yes sir, I have checked to ensure pins 1 & 2 are jumpered together on J5. I'm supplying and CMOS level clock to J8 on the SMA connector. I've also ensured that the PRBSEN  jumper on J7 is removed so that R11 is pulling PRBSEN high.

You mentioned figures 8 & 10 in the appendix A of the user's guide. I'm wondering if I'm working using a different version of the user's guide. Appendix A only has schematics and board layout images. I'm working from the user's guide downloaded from "https://www.ti.com/tool/TLK1501EVM?keyMatch=TLK1501EVM&tisearch=e2eSearch-EN-support#supportandcommunity"  with the date 14, JUN 2000. I'm trying to get figure 2-2 on page 2-4 working. 

I have a short  4" coax cable on connector J13 jumpered to SMA connector J17 and SMA coax cable on J14 connected to SMA connector J23.

I've have connected an oscilloscope to J14 to check for any activity. There is no waveform output observed on the oscilloscope. I have a logic analyzer connected to J3 & J4 to monitor outputs.  

Please advise,

Mike

The user's guide version I'm using is also June 2000. In the appendix you should be able to see "Figure A–8.Top Layer 1". That layer contains the connectors and their part numbers are readable from silkscreen. Can you provide more details on your GTX_CLK input signal?

• Frequency
• Amplitude, Vhigh, Vlow, DC bias level if applicable
• Typical jitter

Regards,

Rodrigo Natal

HSSC Applications engineer

Hi Rodrigo,

The operating frequency of the clock is currently set to 50Mhz. I've tried 30Mhz and 70Mhz with no luck.

The GTX_CLK input clock characteristics are the following:

Amplitude: 3.48v

VHigh : 3.36v

Vlow: -120mv

DC Bias: 1.52v

Jitter: < 80ps - My old O-scope does not have the resolution to measure accurately.

I believe the input clock falls within the specifications defined in the TLK1501 datasheet.

Please advise,

Mike

Hi,

I'm scratching my head as to what might be going on. A couple additional suggestions:

• If you AC couple your clock signal for GTX_CLK does it make a difference?
• Can you measure TESTEN PRBSEN and ENABLE values on your board?

Cordially,

Rodrigo Natal

Hi Rodrigo,

I thought about AC coupling but I'm hesitant because I did not want to damage the GTX_CLK input by dropping below the -0.3volt rating as specified in the datasheet. Do you see any issues if I try an AC coupled Clock?

Using a voltmeter the TESTEN & PRBSEN measure 0 volts. Theses two pins have jumpers on them which ties them both to the ground. 

The ENABLE pin measures ~2.5 volts since it is open.

I place an oscilloscope probe on the pad of R22 to see what the clock looks likes at the GTX-CLK input to the TLK1501.  R21 is not populated but I monitored from the same pad that is connected to R21 & R23.

The clock peak-peak levels significantly drop at that location. The voltage levels drop below CMOS clock specifications. Looking at the resistance value of R23,  which is used as a pulldown/load resistor for the clock circuit, there is a 50 Ohm resistor. Do you see any issues if I remove R23 from the circuit so the loading is removed?

Please advise,

Mike 

Related to: "Do you see any issues if I remove R23 from the circuit so the loading is removed"

• I think it is worth trying it, given that you are seeing significant voltage drop for the clock peak-to-peak level

I would suggest to wait on performing any testing with AC coupled GTX_CLK signal until after you do the above test check first.

Cordially,

Rodrigo Natal

Hi Rodrigo,

I removed the R23 50-ohm resistor. Unfortunately, no luck resolving the problem. Checking the clock levels at GTX_CLK input with an oscilloscope, they appear to be correct. However, there SEDES does not operate.

I do have some good news. Because the SERDES is critical to our project, we purchased a second development board. After hooking it all up to our clock and logic analyzer, the second SERDES board works perfectly. We didn't have to alter anything, the board worked out of the box.  So my suspicions have been confirmed, that we've been fighting with a bad board the whole time. Finally, we can move forward, and try to catch up since these issues set us back a few weeks.

I thank you for all your support & guidance.

I do have one more question, then I'll stop being a nuisance to you. Can you direct me to someone who can help with the replacement of the non-functioning SERDES board?

Take care,

Mike