Hello TI experts,
I have used TMDS181 in my project. I meet a critical issue in my debugging. You can refer to my block design diagram and schematic in the attachment. I can catch a 148.5Mhz clock signal which sent from PC in TMDS181 input side, but I can't catch the clock signal output from TMDS181 in FPGA side. I used pin strap mode in my design.
My configuration as below:
1) SIG_EN ( PIN 17) with a 64.9k resistor pull down
2) I2C_EN_PIN(PIN 10) with a 64.9k resistor pull down
3) OE (PIN 42) with a 4.7K resistor pull up to 3.3V
4) EQ_SE_A0 ( PIN 21 ) NC
5) A1 (PIN 27) NC
6) VSADJ (PIN 22) with a 7.06K resistor pull down
7) TX_TERM_CTL (PIN 36) NC
8) PRE_SEL (PIN 20) NC
9) SWAP_POL (PIN 1) NC
10) SPDIF_N (PIN 45) with a 470K resistor pull down.Intput_card schematic.pdfCard block diagram.pdf
Thanks a lot.