DP83869HM: Media Converter should have any termination Required ?

Hi Mohamed, 

The DP83869 expects a logic low signal from the Signal Detect pin of the SFP when the signal is present in normal operation. I can work to provide a solution to invert the expected polarity of the DP83869 Signal Detect pin and respond in 2-3 days. 

Regards,
Justin 

Hi Mohamed, 

The polarity of Signal Detect pin of the DP83869 can be changed through register 0x0030[2].

0x0030[2]: Signal_detect polarity control bit
0: Invert the polarity of signal detect pin.
1: Use signal detect as is.

Regards,
Justin 

Hi Justin,

Thanks you for your response !!!

In the meanwhile , I was search in datasheet and i didn't get the register details of 0X30.

additionally in datasheet There is no one place mentioned the Signal Detect pin should low for normal operation and high for fault condition.

In previous discussion , I had been attached the schematic for verify the termination resistor. Is that correct ?

please let me know.

Could you please let me know register details of 0X2F and 0X30. it might be more helpful to us.

Thanks and Regards,
Mohamed Sidiq.H

DP83869HM High Immunity 10_100_1000 Ethernet Physical Layer Transceiver With Copper and Fiber Interface datasheet (Rev. A).pdf

Hi Mohamed, 

Can you describe what is needed in register 0x002F? This a reserved register that should not be needed for configuring the device. Register 0x0030 is an internal configuration register. We will share bit 6 on the next revision of the datasheet but the rest of the bits are considered Reserved. 

The termination of the MDI signals and fiber signals in the schematic you shared are correct as well. 

Regards,
Justin 

Hi Justin,

I am extremely sorry for the delayed response ! 

I tried it for the past several days, and found link is not established in the Phy.

Here my observation below:

1. All the power and strap signals found Ok .

2. Crystal clock is 25Mhz. found Ok

3. Phy's Clock out pin measured 25Mhz. found OK

4. Signal detect pin of Phy Side I made directly Ground through 2.49K. I am not doing any register configuration for this.

Please clarify my points,

1. I have used miniature magnetic (ALT3232M-151-T001) is it ok ? Will it match with Phy ?

2. Why the Phy is not linked up ?

Please give me your suggestion ,

Thanks and Regards,

Mohamed Sidiq.H

Hi Justin, 

Thanks for your support.

Finally the Phy had got a link up.

The problem solved , by removing the external strap resistor R42 and R41 (LED1 , LED2) Signals respectively.

We followed the EVM Sch of DP83869 LED1, LED2 made Pull down configuration. (External 2.49 K Pull down) with the jumper option.

Can you clarify, why Phy is not link up when the external strap 2.49K Pull down is used for LED1, LED2 ?

Thanks and Regards,
Mohamed Sidiq.H

Hi Mohamed,

Can you tell me if the setting in register 0x006E, STRAP_STS register, changed when the LED_1, LED_2 pull-down resistors were removed?

Regards,
Justin 

Hi Justin,

I am not changed any of the register.

Thanks and Regards,

Mohamed Sidiq.H

Hi Mohamed,

Can you please share the value in register 0x6E with LED_1, LED_2 removed? I don't expect it to change but the difference you are seeing is not expected. Can you also comment if the LED signals are connected anywhere else in the schematic? 

Regards,
Justin 

Hi Justin,

I didn't have any of the external device to read the Register Details.

The LED_1, LED_2 are not connected to any other device.

Note: JTAG_TDI_SD pin I made it Ground. 

Can you share your email to send the Schematics ?

Thanks and Regards,

Mohamed Sidiq. H

Hi Mohamed, 

You can send it to lazaruk@ti.com. 

Regards,
Justin