Hello team,
Hope you are doing well. When you get a chance please share some feedback on below customer question:
We are trying to implement a design where the SN65DSI83 can be powered off, yet the I2C bus continues to be used for other devices. We believe that the device can be powered off and the SDA/SCL I/O can remain at 1.8V because they are open collector. I expect there are ESD steering diodes that make that a bad idea. Please let us know the I/O structure on the SDA & SCL pins. Also, what is your recommended TI I2C isolation buffer for 1.8V I/O on each side?