DS90UB941AS-Q1: No LVDS output signal with DS90UB941AS-Q1+DS90UB948-Q1

Buridan Zhao

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: ALP

Dear TI Experts:

I am using DS90UB941AS-Q1+DS90UB948-Q1 for MIPI to Dual LVDS display, but cannot found valid LVDS signal output on UB948.

The application as follows, and UB941/UB948 all use the pixel clock:

+-------------+   4 lanes   +-------------+             +-------------+             +-------------+
|        MIPI0|------------>|DSI0     OUT0|------------>|IN0     LVDS0|------------>|   TFT LCD   |
|        I2C17|<----------->|I2C          |  FPD-Link3  |             |  Dual OLDI  |  1920*720   |
|     SOC     |             |    UB941    |   2 lanes   |    UB948    |             |  1280*720   |
|             |             |             |     STP     |             |  No signal  |  1400*900   |
|  1080P MAX  |             |DSI1     OUT1|------------>|IN1     LVDS1|------------>|  1920*1080  |
+-------------+             +-------------+             +-------------+             +-------------+

I just have a demo board which is adapt the current TFT panel(1920*720). So I cannot debugging the board directly with ALP tools but use a shell script as follow:

#!/bin/sh

i2cport=17
seraddr=0x0c
desaddr=0x2e

# Get I2C bus status
i2cdetect -a $i2cport
i2cdump -f -y $i2cport $seraddr

# Config Ser
i2cset -fy $i2cport $seraddr 0x01 0x07 b    # Reset DSI/DIGITLE

sleep 1

i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x03 0xBA b    # Enable I2C pass through

i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x5B 0x03 b    # FPD-Link3 TX mode
i2cset -fy $i2cport $seraddr 0x56 0x00 b    # clock mode
i2cset -fy $i2cport $seraddr 0x4F 0x8C b    # DSI Continuous Clock Mode,DSI 4 lanes

i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x40 0x04 b    # select DSI0 regs
i2cset -fy $i2cport $seraddr 0x41 0x21 b    # DSI_CONFIG_1
i2cset -fy $i2cport $seraddr 0x42 0x60 b    # DSI VS/HS Polarity

i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x40 0x04 b    # select DSI0 regs
i2cset -fy $i2cport $seraddr 0x41 0x05 b    # DPHY_SKIP_TIMING
i2cset -fy $i2cport $seraddr 0x42 0x16 b    # Tskip Count

i2cset -fy $i2cport $seraddr 0x01 0x00 b

sleep 1

# Get I2C bus status
i2cdetect -a $i2cport
i2cdump -f -y $i2cport $seraddr
i2cdump -f -y $i2cport $desaddr

echo Done.

Execute the script after power on the demo board, and the response is:

Probe chips 0x00-0x7f on bus 17? (Y/n):
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: -- -- -- -- -- -- -- -- -- -- -- -- 0c -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- UU -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- UU -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 92 00 00 5c 00 00 01 0e 00 27 30 00 00    ?..?..\..??.'0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00    ...?..?????...?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 10 90 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
50: 16 00 00 00 02 00 00 02 00 00 d9 00 07 06 44 31    ?...?..?..?.??D1
60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
Probe chips 0x00-0x7f on bus 17? (Y/n):
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: -- -- -- -- -- -- -- -- -- -- -- -- 0c -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2e --
30: -- -- -- UU -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- UU -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 ba 00 00 5c 00 00 01 19 00 27 30 00 00    ?..?..\..??.'0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00    ...?..?????...?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 04 05 16 00 00 00 00 00 00 00 00 00 00 00 00 8c    ???............?
50: 16 00 00 00 02 00 00 02 00 00 c9 03 07 06 44 31    ?...?..?..????D1
60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 5c 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    \?.???.?........
10: 00 00 00 00 00 00 00 00 00 01 00 00 33 10 00 00    .........?..3?..
20: 00 00 40 24 08 00 83 84 11 00 00 00 00 00 00 00    ..@$?.???.......
30: 00 00 90 25 01 00 00 c8 00 00 00 03 20 e0 23 00    ..?%?..?...? ?#.
40: 43 03 03 00 60 88 00 00 0f 00 00 08 00 00 63 00    C??.`?..?..?..c.
50: 03 10 00 01 80 00 00 00 00 3f 20 20 00 00 00 00    ??.??....?  ....
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 7d 00 00 00 00 00 00 00 00 00 00 00 00 00    ..}.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
Done.

I did not find a configuration example for UB948 on the forums and documents, and any recommend settings for the UB941/UB948 for the LVDS output problem?

Best Regards,

Buridan

over 5 years ago

0 Casey McCrea over 5 years ago

TI__Guru** 103215 points

Hello Buridan,

Let's first isolate the issue by using the pattern generation features of the serializer to make sure that the link between 941AS->948 is working correctly. Can you please follow this guide to generate a pattern from the 941AS to match your display timing? Please take the following steps:

1. Generate PATGEN from 941AS using internal timing and internal clock (verify functionality)

2. If #1 worked, then use the same pattern but configure the generator to use internal timing and external clock from the DSI source (verify functionality)

3. If #2 worked, then enable pattern generation with external timing and external clock

Please let us know what you find and then we can figure out what to try next based on the results.

Best Regards,

Casey

0 Buridan Zhao over 5 years ago in reply to Casey McCrea

Prodigy 60 points

Dear Casey:

Thanks alot for your help, now I found it does not work at step #3.

#1. It works when use PATGEN with internal timing and internal clock:

... ...
i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x03 0xBA b    # Enable I2C pass through
i2cset -fy $i2cport $seraddr 0x65 0x04 b    # PATGEN_EXTCLK: internal divided clock
                                            # PATGEN_TSEL: Patgen creates its own video timing
i2cset -fy $i2cport $seraddr 0x64 0x05 b    # Enable PATGEN/Colorbar/Checkerboard
... ...

I found that the panel just flashing with colorbar each time when power on the demo board while the backlight is always on since the panel worked once. And I measured that there is no valid LVDS signal output when the panel flashing.

It stoped flashing after execute the script above, but sometimes the pannel color is no longer bright than when it's flashing.

It may be related to the TFT panel and LVDS timing, now I just could judge whether the LCD is working normally by the flashing phenomenon.


     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 ba 00 00 5c 00 00 01 30 00 07 30 00 00    ?..?..\..?0.?0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00    ...?..?????...?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a8 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 04 05 16 00 00 00 00 00 00 00 00 00 00 00 00 8c    ???............?
50: 16 00 00 00 02 00 00 02 00 00 c9 03 07 06 44 19    ?...?..?..????D?
60: 22 02 00 00 05 04 00 00 00 00 00 00 00 00 20 00    "?..??........ .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 5c 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    \?.???.?........
10: 00 00 00 00 00 00 00 00 00 01 00 00 33 10 00 00    .........?..3?..
20: 00 00 40 24 08 00 83 84 11 00 00 00 00 00 00 00    ..@$?.???.......
30: 00 00 90 25 01 00 00 c8 00 00 00 07 20 e0 23 00    ..?%?..?...? ?#.
40: 43 03 03 00 60 88 00 00 0f 00 00 08 00 00 63 00    C??.`?..?..?..c.
50: 03 10 00 01 80 00 00 00 00 3f 20 20 00 00 00 00    ??.??....?  ....
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 7d 00 00 00 00 00 00 00 00 00 00 00 00 00    ..}.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........

#2. It seems worked when use PATGEN with internal timing and external clock:

... ...
i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x03 0xBA b    # Enable I2C pass through
i2cset -fy $i2cport $seraddr 0x65 0x0C b    # PATGEN_EXTCLK: external pixel clock
                                            # PATGEN_TSEL: Patgen creates its own video timing
i2cset -fy $i2cport $seraddr 0x64 0x05 b    # Enable PATGEN/Colorbar/Checkerboard
... ...

When I unplug the MIPI(CLK=150MHz) connector, the panel start flashing(No LVDS signal) and until I plugin the connector. So I think the external clock works.

#3. It seems not work with external timing and external clock:

... ...
i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x03 0xBA b    # Enable I2C pass through
i2cset -fy $i2cport $seraddr 0x65 0x08 b    # PATGEN_EXTCLK: external pixel clock
                                            # PATGEN_TSEL: Patgen uses external video timing
i2cset -fy $i2cport $seraddr 0x64 0x05 b    # Enable PATGEN/Colorbar/Checkerboard
... ...

The panel still flashing(No valid LVDS output) after execute the script above, and the dump data as follow:


     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 ba 00 00 5c 00 00 01 14 00 07 30 00 00    ?..?..\..??.?0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00    ...?..?????...?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 04 05 16 00 00 00 00 00 00 00 00 00 00 00 00 8c    ???............?
50: 16 00 00 00 02 00 00 02 00 00 c9 03 07 06 44 31    ?...?..?..????D1
60: 22 02 00 00 05 08 00 00 00 00 00 00 00 00 20 00    "?..??........ .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 5c 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    \?.???.?........
10: 00 00 00 00 00 00 00 00 00 01 00 00 33 10 00 00    .........?..3?..
20: 00 00 40 24 08 00 83 84 11 00 00 00 00 00 00 00    ..@$?.???.......
30: 00 00 90 25 01 00 00 c8 00 00 00 02 20 e0 23 00    ..?%?..?...? ?#.
40: 43 03 03 00 60 88 00 00 0f 00 00 08 00 00 63 00    C??.`?..?..?..c.
50: 03 10 00 01 80 00 00 00 00 3f 20 20 00 00 00 00    ??.??....?  ....
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 7d 00 00 00 00 00 00 00 00 00 00 00 00 00    ..}.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........

So, what's the next step should I do? Is there any configuration error above?

Best Regards,

Buridan

0 Michael.Walker over 5 years ago in reply to Buridan Zhao

TI__Mastermind 19720 points

Hi Buridan,

Can you check the register DSI_VC_DTYPE in condition 3 to check and make sure the data type is correct. This register is an indirect register please refer to "DSI Port 0 and Port 1 Indirect Registers" on how to read this register.

Regards,

Michael W.

0 Buridan Zhao over 5 years ago in reply to Michael.Walker

Prodigy 60 points

Hi Michael,

With the script function as follow, I dumped the DSI0 and DSI1 registers here after execute the script:

function ser_dsireg_dump(){
    # UB941 device DSI registers dump
    # Args:
    #   $1: port    : 0/1
    port=0x07
    if [ $1 -eq 1 ]; then
        port=0x0B
    fi
    i2cset -fy $i2cport $seraddr 0x40 $port b
    i2cset -fy $i2cport $seraddr 0x41 0x00 b
    echo "Dumped DSI"$1" registers here:"
    echo "     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f"
    for i in $(seq 0 3)
    do
        echo -n $i"0: "
        for j in $(seq 0 15)
        do
            res=`i2cget -fy 17 0x0c 0x42`
            echo -n ${res: 2: 2}" "
        done
        echo " "
    done
}

Dumped DSI0 registers here:
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 00 00 1d 14 16 00 00 00 00 00 00 00 00 00 1f
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 7f 60 ff 7f 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 20 00 04 00 20 00 00 00 00 02 03 00 00 00 00
Dumped DSI1 registers here:
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 00 00 1d 14 3a 00 00 00 00 00 00 00 00 00 10
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 7f 00 ff 7f 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 20 00 04 00 20 00 00 00 00 02 03 00 00 00 00
###

The DSI_VC_DTYPE(0x2A) value is 0x00

0 Michael.Walker over 5 years ago in reply to Buridan Zhao

TI__Mastermind 19720 points

Hi Buridan,

Your TSKIP value might be incorrect, what DSI rates are you using on both channels?

Regards,

Michael W.

0 Buridan Zhao over 5 years ago in reply to Michael.Walker

Prodigy 60 points

Dear Michael:
The DSI0_CLKP clock is about 150MHz that I messured, and the physical size is 1920x1080 with the command: "adb shell wm size". And the DSI1 is not used.

I should have posted the wrong data last time, the result after execute the shell is:

i2cset -fy $i2cport $seraddr 0x01 0x0f b    # Reset DSI/DIGITLE
sleep 1
i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x03 0xBA b    # Enable I2C pass through
i2cset -fy $i2cport $desaddr 0x01 0x03 b    # Reset Des DIGITAL
i2cset -fy $i2cport $seraddr 0x65 0x08 b    # PATGEN_EXTCLK: external pixel clock
                                            # PATGEN_TSEL: Patgen uses external video timing
i2cset -fy $i2cport $seraddr 0x64 0x15 b    # Enable PATGEN/Colorbar/Checkerboard

i2cset -fy $i2cport $seraddr 0x1E 0x01 b
i2cset -fy $i2cport $seraddr 0x5B 0x0B b    # FPD3_TX_MODE=Dual, Align on DE
i2cset -fy $i2cport $seraddr 0x4F 0x8C b    # DSI Continuous Clock Mode,DSI 4 lanes

ser_dsireg_write 0 0x05 0x1E

i2cset -fy $i2cport $seraddr 0x01 0x00 b

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 ba 00 00 5c 00 00 01 1a 00 27 30 00 00    ?..?..\..??.'0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00    ...?..?????...?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 04 05 1e 00 00 00 00 00 00 00 00 00 00 00 00 8c    ???............?
50: 16 00 00 00 02 00 00 02 00 00 c9 0b 07 06 44 31    ?...?..?..????D1
60: 22 02 00 00 15 08 00 00 00 00 00 00 00 00 20 00    "?..??........ .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
Dumped DSI0 registers here:
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 00 00 1d 14 1e 00 00 00 00 00 00 00 00 00 3f
10: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00
20: 7f 00 ff 7f 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 20 00 04 00 20 00 00 00 00 02 03 00 00 00 00

There is a CNTRL_ERR_HSRQST_3 on DSI0 data lane 3. And the UB948 can not output LVDS signal even I tried DPHY_SKIP_TIMING(150MHz=>0x30) from 0x00 to 0x7E.

Best regards,

Buridan

0 Michael.Walker over 5 years ago in reply to Buridan Zhao

TI__Mastermind 19720 points

Hi Buridan,

Can you try setting the TSKIP_CNT register to 0x0A? and run test 3 again?

Regards,

Michael W.

0 Buridan Zhao over 5 years ago in reply to Michael.Walker

Prodigy 60 points

Hi Michael,

There is still no valid LVDS signal output when set TSKIP_CNT=0x0A with the script above but DSI0[0x05]=0x14:

ser_dsireg_write 0 0x05 0x14

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 ba 00 00 5c 00 00 01 23 00 07 30 00 00    ?..?..\..?#.?0..
10: 00 00 00 8b 00 00 fe 1e 7f 7f 01 00 00 00 01 00    ...?..?????...?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 04 05 14 00 00 00 00 00 00 00 00 00 00 00 00 8c    ???............?
50: 16 00 00 00 02 00 00 02 00 00 c9 0b 07 06 44 31    ?...?..?..????D1
60: 22 02 00 00 15 08 00 00 00 00 00 00 00 00 20 00    "?..??........ .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 00    ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
Dumped DSI0 registers here:
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 00 00 1d 14 14 00 00 00 00 00 00 00 00 00 1f
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 7f 00 ff 7f 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 20 00 04 00 20 00 00 00 00 02 03 00 00 00 00

Best regards,

Buridan

0 Michael.Walker over 5 years ago in reply to Buridan Zhao

TI__Mastermind 19720 points

Hi Buridan,

Can you verify that your SOC is outputting LP transitions for every frame of video? what SOC are you using?

Regards,

Michael W.

0 Buridan Zhao over 5 years ago in reply to Michael.Walker

Prodigy 60 points

Hi Michael,

The SOC is NXP IMX8QXP(https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-8quadxplus-multisensory-enablement-kit-mek:MCIMX8QXP-CPU).

I made a mistake on the MIPI0 port abot output data type, I should use MIPI-DSI but the actual output is OpenLDI. And I will try the MIPI-DSI output in the next few days.

Best Regards,

Buridan

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