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TUSB4020BI: Question Regarding datasheet of TUSB4020BI

user6400773
Prodigy 30 points
Part Number: TUSB4020BI

Dear Sir or Madam

I have four questions regarding the data sheet.

No.1
The USB hub data sheet describes how to design a 24MHz input by the resonator for input to the XI pin.
When inputting 24MHz with an oscillator, is it OK to think that the conditions for PPM (±100) and load capacitance (12-24pF) are the same as for the oscillator?
No,2
When inputting 24MHz to the HSB hub (XI pin) with an oscillator, is there a clock input timing regulation?
(Example: Input after VDD input, but before GRSTz rise.)
In addition, it seems that the data sheet for the USB hub only described the PowerON sequence as shown in the figure on the right. Please let me know if there is a regulation of Power OFF.
No.3
We are planning to connect the oscillator described in PDF to the HSB hub and input 24MHz.
I was unable to read the slew rate or voltage level for the oscillator from the HSU hub data sheet.
Please let us know if this oscillator meets the HUB hub standards (whether the slew rate or voltage level is acceptable).
No,4
As for the signal input timing to the USB hub (USB_VBUS pin), is it OK to use the signal input at the timing when VDD33, VDD, and GRSTz all rise?
Please let me know if you have any regulations regarding communication start timing.
I look forward to hearing from you soon.
Yours sincerely,
Yoshinori
  • 0
    TI__Guru 60870 points

    Hello Yoshinori,

    1. Yes, the PPM conditions for the oscillator are the same as for the crystal.  The load capacitance requirements are determined by the crystal or oscillator not the hub.

    2. There are no power off regulations.  The clock must start before the end of reset, I would recommend at least 100 us before the end of reset.

    3.  Oscillator must be 1.8V   The link did not appear, can you resend it?

    4. The USB_VBUS input is a detection input, it should only be high when a powered, active upstream connection is there.  The hub may run into interoperability issues if USB_VBUS is tied to a power rail.

    Regards,

    JMMN

  • 0 in reply to JMMN
    Prodigy 30 points
    Thank you for your reply JMMN.
    I have additional questions.
    1. confirmed. Thank you
    2. confirmed. Thank you
    3. I'm sorry.
     I will send you a link.
    4. Thanking for pointing that out.
    I understand that USB_VBUS goes high when there is upstream.
    Is it okay if the timing when the upstream goes high is the timing when VDD33, VDD, and GRSTz all rise?
    USB_VBUS is started by PCONT signal. It does not connect to the power rails, so there are no interoperability issues.
    I look forward to hearing from you soon.
    Yoshinori
  • 0 in reply to user6400773
    TI__Guru 60870 points

    Hello Yoshinori,

    #3 Slew rate is fine, voltage level is ok as long as they use the 1.8V option.

    #4. Timing sounds acceptable, as long as USB_VBUS is not high when the host controller is disabled or before it is ready to start USB 3.0 receiver detect.

    Regards,

    JMMN

  • 0 in reply to JMMN
    Prodigy 30 points

    Hello JMMN

    I'm sorry for the last reply.

    I understood your explanation !
    Thank you very much.

    Yohsinori