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TLK10002: TLK10002

Part Number: TLK10002
Other Parts Discussed in Thread: TLK10034, TLK10031, TLK10232

We want to provide a 9.8 Gbps CPRI link towards the RRH. However, we know that the AIF2 interface on the TMS320TCI6638 can support only upto 4.9 Gbps. We want to combine the two AIF2 interfaces available from each DSP SoC and provide a 9.8 Gbps CPRI link. We are looking at TLK10002 for this purpose. We have three DSP SoCs for which this CPRI rate combining is to be done on the same RAC card.

 

Clarity required:

1. Since TLK10002 has two channels, do we need two devices to cater to the three DSP SoCs on the RAC card?

2. Is there any other equivalent device that you recommend, - is there a variant of this device which supports three channels so that we need to use only one device per RAC card?

  • Hi, see my inputs below.

    1. Since TLK10002 has two channels, do we need two devices to cater to the three DSP SoCs on the RAC card?

      • You would need two devices, if using this two channel variant. TI does also have a quad 10G transceiver available

    2. Is there any other equivalent device that you recommend, - is there a variant of this device which supports three channels so that we need to use only one device per RAC card?

      • You may also consider the following part numbers. All of these part numbers “Supports Multi-Rate SERDES Operation with up to 10.3125 Gbps Data Rate on the High Speed Side and up to 5 Gbps on the Low Speed Side”

        1. TLK10034 Quad-Channel XAUI/10GBASE-KR Transceiver

        2. TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

        3. TLK10232 DUAL-CHANNEL XAUI/10GBASE-KR TRANSCEIVER WITH CROSSPOINT

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Thanks for the clarifications, Rodrigo.

    Is there any proprietary implementation on the TLK10002 or TK10003x transceivers that will necessitate the same transceivers to be used on both ends of the link ?  We want to implement this as a CPRI combiner at the baseband end (connected at the low speed end to the K2K processor's two AIF2 interface) and connected over the CPRI interface on the high speed end to a Radio Head, which does not use the TLK device, but implements the CPRI interface using SerDes of an FPGA. Do you foresee any compatibility issues?

    Regards

    Sivan R

  • No, not that I'm aware of. I do not foresee compatibility issues.

    Cordially,

    Rodrigo Natal

  • Thanks, Rodrigo.

    Considering the TLK10034 in our design, with two AIF2 lanes of the TCI6638 connected to Low Speed Side of TLK10034, to provide a 9.8 Gbps link on the High Speed Side. Using the AIF2 in CPRI mode.

    I am not clear about how the C&M channel of CPRI will be mapped in the High Speed Side. I wish to send the C&M packets only through one of the two AIF2 lanes. How is that acheived? Could not find any documentation that can clarify this. Request support on this.

    Regards

    Sivan Ramachandran

  • Hi,

    Please refer to Section 5.3.3.8 "Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode" of the TLK10034 datasheet and refer to Table 5.4. You would want to use the low-speed side settings for 4915.2 line rate and high-speed settings for 9830.4 line rate.

    Table 5-4. Specific Line Rate and Reference Clock Selection for the 2:1 General Purpose Operation Mode

    LOW SPEED SIDE

    HIGH SPEED SIDE

    Line Rate

    (Mbps)

    SERDES PLL Multiplier

    Rate

    REFCLKP/N (MHz)

    Line Rate

    (Mbps)

    SERDES PLL Multiplier

    Rate

    REFCLKP/N (MHz)

    4915.2

    20

    Full

    122.88

    9830.4

    20

    Full

    122.88

    3840

    12.5

    Full

    153.6

    7680

    12.5

    Full

    153.6

    3072

    10

    Full

    153.6

    6144

    10

    Full

    153.6

    2457.6

    8/10

    Full

    153.6/122.88

    4915.2

    16/20

    Half

    153.6/122.88

    1920

    12.5

    Half

    153.6

    3840

    12.5

    Half

    153.6

    1536

    10

    Half

    153.6

    3072

    10

    Half

    153.6

    1228.8

    8/10

    Half

    153.6/122.88

    2457.6

    16/20

    Quarter

    153.6/122.88

    768

    10

    Quarter

    153.6

    1536

    10

    Quarter

    153.6

    614.4

    8/10

    Quarter

    153.6/122.88

    1228.8

    16/20

    Eighth

    153.6/122.88

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer