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DP83869HM: DP83869HM RGMII and MII configurations

user5350137
Intellectual 520 points
Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Hi,

I am using DP83869HM developing a HUB, and I am struggling in PHY debug for days, and I didn't figure out the root reason. Can you help me on below questions to make me clear about physical layer work?

1. In MII and RGMII mode, Is TXCLK, XI and RXCLK in same clock domain? I want to use same PHY device to transmit its received data, do I need to use FIFO for different clock data sync in my FPGA code?

2. Which clk edge(rising or falling edge) I should use to lock RX and TX data in MII mode? And how about RGMII mode?

3. How to configure as MII mode? In MII mode, how to configure GTXCLK/TXCLK pin to TXCLK? Or it will automatically be TXCLK in MII mode?

4. If I use MII mode, TXCLK should be output from DP83869, is it sync with XI clk? If yes, can I just use XI clk to lock my TX_data? 

5. If I use RGMII mode and only need 100base-Tx, TXCLK should be input to DP83869, can I only use one clk source(from FPGA) to drive XI and TXCLK pin? 

6. How can I verify DP83869HM physical layer is working good? Can link up status show everything good in physical layer?

Many thanks!

Rachel

  • 0
    TI__Expert 7040 points

    Hi Rachel,

    1. The PHY needs 25MHz input clock on XI in all modes. This should come from a crystal or external oscillator. In RGMII, the RX_CLK is generated by the PHY and TX_CLK is generated by the MAC, or FPGA. In MII mode, the PHY generates both RX_CLK and TX_CLK to provide to the MAC interface. 

    2. In MII mode, the data should be captured on the rising edge of TX_CLK, In RGMII the data is captured on the falling edge. 

    3. When the PHY is set to MII mode, the MAC pins will be configured properly. To configure to MII, see register 0x1DF[5] to select between RGMII and MII.

    4. When the PHY is configured in MII mode, the XI pin is not sync'd with the TX_Data pins, you need to use TX_CLK.

    5. No, XI and TX_CLK should be separate inputs to the DP83869. 

    6. The Link Status will show that the PHY is linked to it's link partner over the MDI, it will not provide the status of the MAC interface. Using digital or analog loopback in register 0x0016 can provide a way to verify the MAC interface timing is correctly implemented. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Expert 7040 points

    Hi Rachel,

    I am closing this thread since I have not heard a response. If you need assistance, please create a new post and reference this thread.

    Regards,
    Justin