• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 556 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: Built-In Self Test Not Sending Packets

Matthew Morawiec
Prodigy 80 points
Part Number: DP83867E


Hello, I am trying to use the built-in self test feature in order to test the PHYs in my design. I have read through the datasheet and I understand how to set up the self test. However, I can not seem to get the PRBS to send anything?

This is what I am doing.

1) Set BICSR2 bit #1 to 1 to clear the values PRBS_ERR_CNT and PRBS_BYTE_CNT

2) Set BISCR to 0xD008

-PRBS Continuous mode ON

-Generate continuous packets

-Enable PRBS generator

-Analog loopback mode

3) Set BMCR to 0x0140 (disable Auto-Negotiation)

4) Set CTRL to 0x4000 (Software Restart)

Then, I wait some time and then check the PRBS count and error registers.

For some reason, I see 0 in both PRBS_ERR_CNT and also 0 in PRBS_BYTE_CNT.

Is there some setting I am missing here in order to get this to work? It seems like the PRBS is not generating any bits. I thought you could just set the loopback to analog mode, which is internal, and then turn the PRBS generation on and loop some packets...

Any suggestions would be very helpful!

Thanks

Matt

  • 0
    TI__Expert 7040 points

    Hi Matthew, 

    The steps you are following in enabling the loopback mode are correct. When using analog loopback on the DP83867, please verify that there is 100ohm termination present on the MDI channels. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 80 points

    Hello Justin, thanks for the reply.

    Do you mean fitting external 100 ohm terminations to the MDI pins at the interface connector?

    I am developing this test as a part of a larger board self test. For the test, the PHY will be connected to a network, as I want to check link status. So it would not be possible to terminate the MDI pins. 

    I tried switching to digital loopback mode with the same result. The PRBS_BYTE_CNT still shows zero... 

    What am I doing wrong that the PRBS checker is not receiving anything at all?

  • 0 in reply to Matthew Morawiec
    TI__Expert 7040 points

    Hi Matthew,

    Yes, the PHY needs an external 100ohm termination on the MDI pins. If the PHY is connected to a network, the 100ohm termination should be present at the receiver end of the link partner. 

    Can you also try disabling auto-MDIX and setting MDI or MDIX mode manually? 

    0x0010 = 0x5008 // 5008 - mdi , 5028 - mdix

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 80 points

    Hi Justin,

    I have tried disabling auto-MDIX and setting both MDI and MDIX mode manually with no change. I also terminated each pair with 100 ohms and reran the test with no change as well.

    I don't think termination is the problem... Even if the termination is wrong, it should show that it is transmitting bits and receiving something, even if there are errors due to incorrect termination. 

    EDIT: I have confirmed that, during the test, the packet generator is busy and that the PRBS checker is locked to the bit stream. After the test, BICSR2 reads 0000 0010 0000 0000, indicating a PRBS_BYTE_CNT overflow. At no point in the test do I read anything except 0 in PRBS_BYTE_CNT...

    I tried moving on to TDR and I am having a similar problem there as well... I start the test and the CFG3 register says the test is done, but when I read the TDR_PEAKS_LOC and TDR_PEAKS_AMP registers, they are all zero!

    Why is it that I can "start" the tests but they don't actually do anything?

  • 0 in reply to Matthew Morawiec
    TI__Expert 7040 points

    Hi Matthew,

    The PRBS_BYTE_CNT is latched every write to bit[0] of register 0x0072. Please write to this bit before measuring the byte counter to latch the current counter values. 

    When running the TDR test for the DP83867E, can you provide the register value of CFG3 after TDR is done?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 80 points

    Hi Justin,

    Is that what the datasheet means when it says a write to bit [0] of 0x0072 "generates a lock signal for the PRBS counters"... I though "lock" meant that the value would NOT change if a write was performed on this bit. How confusing... But i will try that.

    The CFG3 register reads 0b0000 0000 0000 0010 once TDR is done

    Thanks,

    Matt

  • 0 in reply to Matthew Morawiec
    TI__Expert 7040 points

    Hi Matt, 

    I understand your confusion. I can confirm that PRBS_BYTE_CNT is latched every write to bit[0] of register 0x0072. 

    Can you also confirm how you are starting the TDR operation?

    Regards,
    Justin