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TLK2711-SP: Why do RKLSB and RKMSB rise irrationally?

秘人大叔 神
Prodigy 40 points
Part Number: TLK2711-SP

I'm using TLK2711A chip on a small circuit board to receive the high speed serial signal output by TLK2711-SP on another circuit board.

The PRBS test has passed. The problems is RKLSB and RKMSB of TLK2711A sometimes rise to 1 randomly.

Here is the schematic of the TLK2711A design:

TLK2711A_V2.pdf

and here is the schematic of the TLK2711-SP design:

G6_07_TLK2711.pdf

We wrongly connected one VDD pin to the GND in the TLK2711-SP design. We've already fixed this error.

Other notes:

1. All the related signals are connected to the GPIO of FPGA.

2. The recovered 100MHz clock can be detected on oscilloscope.

3. we are using dc coupling.

4. We are sure that TKLSB and TKMSB of TLK2711-SP will not rise to 1 erratically, but the RKLSB and RKMSB will rise to 1 erratically.

Can you give us some hints as to where to check? Thank you very much. 

  • 0
    TI__Mastermind 19235 points

    Request noted. We will target to provide some feedback by early next week.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 40 points

    thank you very much!

  • 0
    Prodigy 40 points


    in addition ，PRBS test is right .When using PRBS mode, RXLSB is always 1

  • 0 in reply to 秘人大叔 神
    TI__Mastermind 19235 points

    Hi,

    Sorry for the delay. When your test is performed what type of data is being transmitted? I presume you are passing standard packets with regular comma characters? See excerpt below from previous E2E post.

    The TLK2711 as specified will achieve a BER of 1E-12 or better. This means there could be a single bit error in 10^12 bits. This bit error could cause loss of synchronization. The one way to get synchronized again, is with the comma.

    The TLK2711 is very similar to fiber channel, and can receive valid FC data. It cannot transmit valid FC data due to unique running disparity changes FC employs.

    Fibre Channel frames typically have a maximum payload size of 2112, and with with headers makes the MTU 2148 bytes. However you can increase the payload up to 9000 bytes, and with headers that 9036 bytes.


    Cordially,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 40 points

    Thanks for the information provided. I really appreciated that.

    I've already solved that problem by implementing two methods listed below.

    1. used more reliable cable that has ground shield for the differential signals.

    2. replaced the FPGA's system clock from 50MHz oscillator to 100MHz oscillator. When we were using 50MHz oscillator, the 100MHz clock fed to the TLK2711 was generated by PLL of kintex7. It seems like its peak-to-peak jitter (121.630 ps) is greater than the required jitter (40 ps), which is listed on page 10 of the datasheet. After we used 100MHz oscillator and directly feed it into TLK2711 through the FPGA (bypassing PLL). TLK2711 began to work perfectly.