TUSB522P: Mounting surface about USB3 connector and IC

Hi Saito-san,

The IC and USB connector are typically placed both on the top layer to avoid additional vias. Also it is correct to connect the TX pins of TUSB522P and connectors SSTX. You can refer to the EVM layout and schematic for an example. 

Hi Maik-san,

Thanks. Regarding datasheet layout example, it looks the IC and connector are placed on different layer.  I think it's because of simplicity of the trace.

Customer is concerned below two points in this recommend layout .

1) Whether can IC and connector be placed on different layer?

2) TX1N connects to SSTX+ in the recommend layout. Is that no problem? 

I would appreciate it if you could give me advice about customer's concersns.

Regards,

Saito

Hi Saito-san,

Yes, device trace and connector can be placed on different layers. TX1 to SSTX is correct, Pin 9 and 8 connect to the SSRX on Type-B connector.  

Hi Malik-san,

Thanks. How about the polarity? Is it no problem to connect TX1N to SSTX+ like the layout example? 

Regards,

Saito

Hi Malik-san,

I understand. So, I think the layout example in datasheet is wrong because the polarity is inverted. (TX1N->SSTX+, TX1P->SSTX-)

Anyway, I will ask customer to follow the EVM layout.

Regards,

Saito

Hi Saito-san,

Polarity swap in datasheet is okay as all USB 3 receivers support polarity inversion. EVM layout is a good example to follow. 

Hi Malik-san,

Sorry for my mis-reading.

I understood both layout in datasheet and EVM user guide are correct.

I will recommend both of them to customer. Thank you for your kind support.

Regards,

Saito