DP83867IR: Each loopback test fails at 100Base-TX GMII

Hi gf,

Loopback settings are available in our troubleshooting application note. Please review the register writes and let me know if you still are running into issues.

I will be happy to help if that is the case.

Link: https://www.ti.com/lit/an/snla246a/snla246a.pdf

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

Yes, I already checked the troubleshooting application note.
But there are only digital loopback example.
We also need to know MII and Analog loopback mode of 100Base-TX GMII.
So, could you tell me the setting procedure for MII and Analog loopback?

And as I asked at previous post, does DP83867 also need 100ohm termination
as DP83822 in Analog loopback mode?

By the way, my customer tested MII loopback mode by setting procedure which I wrote at above,
but they still running into this issue.

best regards,
g.f.

Hi gf,

Yes for analog loopback you will require the 100 ohm termination.

Here is the script for it: 

00FE = E720

0000 = 0140

0010 = 5008

0016 = 0008

For MII loopback you will not need to configure 00FE and just update reg 0x0016 for MII loopback instead.

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

I have a few question about the script which you attached.

Don't you need to make reset by setting 1 to Reg:0x001F bit[15] at first step?
And don't you need to set 1 to Reg:0x001F bit[14](Software Restart) after setting 0xE720 to Reg:0x00FE?

By the way, our customer are trying each loopback(MII/Analog/Digital) test
of 100Base-TX GMII by following sequence.
Is there any problem in this sequence?
---------------------------------------------------
Step1.
Set 0x0000 to Reg:0x0032(RGMIICTL) //Disable RGMII

Step2
Set 0 to bit[6] of Reg:0x0043(100CR)

Step3
Set 0 to following bit of Reg:0x0010(PHYCR)
*CR_FORCELINK_GOOD(bit[10])
*MDI_CROSSOVER(bit[6],bit[5])

Step4
Set 1 to bit[10] of Reg:0x0010(PHYCR)

Step5
Set 0 to all bit of Reg:0x0000(BMCR) except bit[10](ISOLATE) and bit[14](LOOPBACK).

Step6
Set 1 to bit[13] and bit[8] of Reg:0x0000(BMCR)

Step7
Set 1 to bit[6](100CR_FORCE_100_OK) of Reg:0x0043(100CR).

Step8
Set 0 to bit[6] and bit[5] of Reg:0x0010(PHYCR) //

Step9
Set 0x0008(for Analog loop) or 0x0004(for Digital Loop) to Reg:0x0016(BISR).
If MII loop mode, set 0x0000 to Reg:0x0016(BISR).

Step10
Set 0xE720 to Reg:0x00FE(LOOPCR)

Step11
Set 0x4000 to Reg:0x001F(CTRL) //Software Restart

Step12
Set 1 to bit[14](LOOPBACK) of Reg:0x0000(BMCR)
////////////////////////////////////////////////////

best regards,
g.f.

Hi gf,

you are correct.You can do the hardware reset FIRST STEP 0x1f = 0x8000 then software reset 0x1f = 0x4000 as LAST step. 

Hi Cecilia,

Thank you for the reply and sorry for the delay.

I have an update about the issue.
The analog and digital loopback issue have been solved.
They were setting BMCR(0x0000)bit[14] "LOOPBACK" to 1 and
this caused the problem.
So, after they changed this bit to '0', the issue have been solved.

But they still having a problem with MII loopback test.
They are requesting the recommended setting sequence for 100Mbps GMII MII loopback.
Is following sequence which you provide us at above post are recommended sequence
for <100Mbps GMII Fullduplex> MII Loopback test?

****************************************
//00FE = E720 (not needed for MII loopback)

0000 = 2100 (select 100Mbps, Full duplex)

0010 = 5008

0016 = 0000

Also add software reset at first step and restart at end of step.
****************************************

And my customer have following questions:

Q.
Software reset(Reg:0x001F bit[15]) and Software restart(Reg:0x001F bit[14])
are "self cleared" function.
How long does it take to be cleared after setting software reset and restart?

best regards,
g.f.

Hi gf,

For GMII/MII loopback in 100M mode, the auto-mdix function must be disabled and no link partner connected.

Have you confirmed this?

The timing diagrams for our resets are available in our datasheets.

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

They are disabling Auto-MDIX and no link partner are connected.

In the datasheet, there are only hardware reset timing diagram.
But we are asking about software reset and restart which is applied by
setting Control Register(addr:0x001F) bit[15] and [bit[14].
As this bits are "self-cleared", we want to know when this bit will be cleared
after setting it to '1'.

And as I mentioned previous post, we want to know recommended settings and sequence for 100Base-TX GMII Fullduplex MII Loopback test.
I need to answer to my customer, so could you please provide us TI's recommended settings and sequence?

best regards,
g.f.

Hi gf,

Write register 0x001F to 0x8000 to apply a software reset.

Write register 0x0032 to 0x0000 enable GMII

Write register 0x0000 to 0x6100 to enable MII loopback.

Write register 0x001F to 0x4000 to apply a software restart.

The setting looks to be the same as your first so I will have to review with our internal team to confirm but this is the sequence i would recommend.

What is more interesting is that digital and analog loopback both work which is a deeper loopback. If these two work then the MII blocks should not have a problem.

As for the reset, I believe it follows the same timing as the hardware. 

Hi Cecilia,

Thank you for the reply.

Yes,your reccommend sequence seems it is same as our first.
If you done confirming with your internal team, please let us know.

And I would like to ask about self-clear timing of "software reset and restart"
to make me sure.
I checked the "7.7 RESET TIMING" written in datasheet page.18 and
I'm guessing that the timing of
"T2 Hardware Configuration latch-in time from the deassertion of RESET" and
"Self-clear" of Control Register bit[15](reset) bit[14](restart) are
equalvalent, is it correct?
What I'm saying is that Control Register bit[15][14] will be
cleared automatically after 120ns when bit[15]or[14] have been set, is it correct?
I need to answer the customer, so please let me know as a product specification.

best regards,
g.f.

Hi gf

Yes that is correct. And I am currently asking our internal team and will get back to you as soon as I gather more info from them on the loopbacks.

Thanks,

Cecilia

Hi gf,

Just received an update. Looks like you also need to configure register 0x10 as well. From our team:

0010 <- 5008

addr:0x0000 value:0x6100 //programs DUT to 100BASE-TX mode and enables MII Loopback

0x0032 value:0x0000 //Configuration for GMII

Please let me know if that works for you. 

Hi Cecilia,

Thank you for an update.
My customer tested with configuring register 0x10(value 0x5008)and also
adding Software reset(via reg:0x001F) at first step and Software restart(via reg:0x001F)
at end of the step.
But the result was same. The problem didn't solved.
Should they delete the reset and restart steps?

The following is the steps they tested:
****************************************************************
addr:0x001F, value:0x8000 //Software Reset

addr:0x0010, value:0x5008

addr:0x0000, value:0x6100 //programs DUT to 100BASE-TX mode and enables MII Loopback

addr:0x0032, value:0x0000 //Configuration for GMII

addr:0x001F, value:0x4000 //Software Restart
****************************************************************

And are there anything else to try?

best regards,
g.f.

Hi gf,

Thank you for the update. This is interesting and will have to confirm with my team again and see if there is anything else you may try.

Thanks very much for your patience. 

Best,

Cecilia

Hi gf,

Thanks for your patience. This is the feedback I received from my team internally:

"As I can see below customer is actually trying to do MII loopback in MII mode (100M), GMII refers to 1G. MII loopback will not work in this configuration if configured in MII mode." 

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

But I couldn't understand about the answer you gave me.
In page.42 "Table 3. Loopback Availability" of DP83867IR datasheet,
it' written as MII Loopback mode is available mode in 100M (MAC I/F GMII) and also 10M.
The customer also tested MII Loopback mode in 10M GMII I/F and the MII Loopback test
have finished with no problem.

So, I guess the customer will not be convinced by the answer you send.

best regards,
g.f.

Hi Cecilia,

I have additional information.
The customer are using two DP83867IR on their board.
GMII are used in one phy and RGMII are used in another PHY.
They also testing MII Loopback with 100M RGMII configuration and no problem have occured.

best regards,
g.f.

Hi gf,

Thanks for the additional information. It looks like when configuring in GMII or MII mode, there are some extra registers that need to be configured for MII loopback and not other loopback modes. 
Because the clocking is also different for RGMII and GMII, MII loopback on RGMII also works differently and does not require these extra registers. Can you please try configuring the items below now?

I believe the major change is updating register 0x16

0x32 = 0x0000
0x1DF = 0x0060
0x10 = 0x5008
0x0 = 0x6100
0x0016 = 0x0004
addr:0x001F, value:0x4000 //Software Restart

Hi Cecilia,

Thank you for the update.

But are you sure to set the value 0x0004 to Addr:0x0016 ?
This configuration will set the loopback mode to digital loopback, isn't it?

And what is "0x1DF = 0x0060" ? Is Addr:0x1DF are secret register and
do you mean that it need to be set for MII loopback mode in GMII 100Base-TX?

best regards,
g.f.

Hi Cecilia,

Do you have any update against my previous post?

best regards,
g.f.

Hi gf,

Apologies on the delay. I was out of the office for one week and could not respond to E2E threads. You are correct these are hidden registers that need to be updated and shared during our next datasheet revision. Do you have any updates on whether or not this solved the MII loopback?

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

I have no update from my customer yet.

In your previous post, it was written as BISCR(Addr:0x0016) need to be set to 0x0004.
But setting 0x0004 to the BISCR will be Digital loopback.
Is this setting necessary to do MII loopback test?
I want to be sure about above question before telling to the customer.

best regards,
g.f.

Hi gf that is correct. 

This looks to be a register configuration that also requires that digital loopback enabled even though it is in MII loopback enabled as well. 

Hi Cecilia,

Thank you for the reply.
Okay, I will tell my customer that they also need to set 0x0016 reg to 0x0004.

I'm very sorry but I have additional question about configuration of hidden register 0x01DF.
I understood that 0x01DF register need to be set to 0x0060.
Is this setting always necessary for MII loopback or does it depend to the device lot?
Because, it seems that the problem may have a possibility of lot dependency.
The customer are using DP83867IR from before, but they never had this problem at the loopback test.
But at their new device lot, the problem occurs.
So, we want to know this register settings either depend to the device lot or not.

best regards,
g.f.

Hi gf,

For RGMII and SGMII as you have mentioned this issue is not seen for loopbacks which is why you may have not seen this in the past. This is due to the fact that internally the clocking is different for these interfaces. 

So this setting and script suggestion above is only needed when using GMII or MII with MII loopback. All other loopbacks as you have seen also work ok and does not require these register changes. 

Please let me know if this clarifies this more for you. 

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

I understood. I'm asking to the customer to try the setup which you shared us previously.
Please wait for the result.

best regards,
g.f.

Hi gf,

Ok thanks for the reply please let us know the results.

Thanks!

Cecilia

Hi Cecilia,

Our customer have following questions, so could you support us?

Q1.
The question is about the hidden register 0x01D which need to be set for MII loopback of MII/GMII.
Is the hidden register 0x01D an extended register?
If yes, could you tell us the sequence of setting the register 0x01D?
If it is not an extended register, do we just set the value as follow example?
==============================
*(volatile unsigned int*)0x01D = value
==============================

Q2.
We understood that hidden register 0x01D will be updated in next revision datasheet.
The customer want to check if the register 0x01D have been set correctly,
so could you share the next revision datasheet before it will going to be released?

Q3.
The customer are planning to start the next development of another product,
and this DP83867IR is also one of the candidates for adoption.
They will select which PHY to be used in the product by using data sheet, etc.,
so they would like to consider by using the latest data sheet of DP83867IR.
Could you tell us when the next revision datasheet of DP83867IR will be released?

best regards,
g.f.

Hi gf,

Thank you for your questions. Let me get back to you by EOD Wednesday on your queries.

Thanks,

Cecilia

Hi Cecilia,

Thank you for supporting us.
Okay, I will wait for the reply from you.

best regards,
g.f.

Hi gf,

Hope you are doing well. Apologies as there was a misunderstanding from my end internally on some of the register configurations. It looks like you may actually ignore register 0x1DF as I misintepreted from my team that it should only be a register configuration for the DP83869 NOT the DP83867. 

Therefore these changes are not actually required on the datasheet. The only thing you need to note is that because of the clocking you will be required to enable digital loopback to run the testing.

Please let me know if you have follow up questions that I can clear up for you.

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

As I already told you that enabling MII Loopback in BMCR(bit[14]) and enabling
digital loopback at same time, the problem will occur.
So, should they stop using MII loopback test?

I understood that configuration of 0x01DF is only needed for other device DP83869 and
so that datasheet won't be updated for this register.
But do you have any schedule for releasing next revision of DP83867IR datasheet?
Because as I said previously, my customer are planning to use DP83867IR for
their next new product and they want to confirm the specification by using latest datasheet.

best regard,
g.f.

Hi gf,

Yes my recommendation is to test loopback using the other modes besides MII loopback if that is alright. 

What is the timeline you require for the new product? I will have to reach out to our editing team to see when we can deliver. However it would be good to know what kind of timeline you are expecting as well.

Thanks,

Cecilia

Hi Cecilia,

Thank you for the reply.

>What is the timeline you require for the new product?
>I will have to reach out to our editing team to see when we can deliver.
>However it would be good to know what kind of timeline you are expecting as well.

Their timeline is end of January 2021.
Could you also please let us know if there are plan to update the datasheet of DP83867IR or not.

best regards,
g.f.

Hi gf,

Ok, thanks for the update I will let you know if we will have an updated datasheet by the end of this quarter.

Thanks,

Cecilia

Hi Jimmy,

Looks like the team’s target is to release a new datasheet revision by 1Q21

Thanks

Cecilia

Hi Cecilia,

If a new datasheet revision going to be released in 1Q21,
is it available to share us preliminary version in advance at the end of 4Q20,
because our customer are requiring?

best regards,
g.f.

Hi gf,

Cecilia is currently out of office and will get back to your question on Monday.

Regards,

Adrian Kam

Hi gf,

Thanks for your patience. I have provided to you the update for the loopback scripts and hope that is helpful enough for your customer to understand when to use which depending on testing. Currently the target for release is 1Q21 however I do believe our current datasheet should still be substantial for new designs.

I am wondering what exactly are you looking for in an updated datasheet that the customer is requiring? Hopefully there are items that can be covered or you may start a new thread if there are parts of the datasheet that are unclear.

Thank you,

Cecilia