DP83826I: Configuration Straps

Hi Dan,

I'll need another day to review all of your questions as it is not as simple as one answer for all.

In the meantime  can you confirm with your customer if they are using BASIC or ENHANCED mode for the DP83826? 

Thanks,

Cecilia

The Basic mode.  This is the first time we have integrated Ethernet functionality so I thought it would be prudent to choose Basic mode. However, we appreciate your advice.

Hi Dan,

I think it depends on the features you are interested in. Section 5 Mode Comparison Tables highlights the differences between the two modes so let me know if these differences help you decide with your customer on their preferences. 

I would recommend using ENHANCED as there are more strapping options as well as RMII b2b repeater mode if your customer is interested in that as well. 

From customer:

We studied section 5. We would like to continue with Basic mode. Please continue with this original mode selection to respond to our questions from August 28th.

Table from datasheet:

As above, in many places on these pages in the datasheet I see a "DEFAULT" column. However, I would think the internal pull resistors in the above example would actually 'default' the above example parameter PHY_ADD to 000 not 001.

> What do the "DEFAULT" column values mean?

Default is the mode after power up and RST have occurred. Once the PHY identifies the mode (basic or enhanced) it will default to the states mentioned in the strap configuration table

> In what condition(s) does this "DEFAULT" value for the PHY Address PHY_ADD occur since it does not seem to agree with the internal pull resistors ( internal pull resistors would result in 000 )?

The internal pull down as mentioned in the pin mapping is only for reset. As mentioned above once in basic or enhanced mode the PHY will default to respective modes

For the pins RX_D3, RX_D2:

> Once RMII Slave Mode ( Strap 10,3,4 = 1,0,1 ) is latched what is the state of RX_D3 and RX_D2?

In BASIC mode these straps are defaulted to mode 1 and 0 if these pins are left open

> We are asking because if RX_D3 and RX_D2 become / stay tristate ( I,PD ) we could simply short RX_D3 and RX_D2 to Vdd or GND as needed instead of requiring a resistor to limit the current.

No need to short as they have the internal pull down resistors that should drive it out of a tri state mode.

> Please advise if in the RMII Slave Mode it is ok to short RX_D3 and RX_D2 to Vdd.

We do not recommend shorting these pins to gnd

Will need to confirm the correct strap configurations for RMII Slave Mode for last question 

4.

• CEXT specifies a 2nF capacitor must be attached, however as far as I can find no tolerance or other data is specified.
• Is this a critical capacitance?
• If not, could a 0.1µF capacitor be used instead?  
• What is CEXT used for?

We also look forward to hearing about #3 from 8/28. Copied below for convenience.

3. To minimize board space and BOM it would be ideal to set the MAC Mode to RMII Slave Mode by SMI/MDIO instead of straps.

> Because the XI clock is configured by straps and is supplied by a 3.3V CMOS 50 MHz clock supplied by the main microcontroller (slave mode), we imagine the DP83826 would not have a clock upon strap latch. If we understand correctly from the datasheet the DP83826 will latch as "MII MAC mode" with its internal pulls alone for straps 10,3,4.  Is it possible to access the SMI/MDIO interface when the XI has no clock?

> Please advise us if the following is the correct configuration if configuring the MAC Mode for RMII Slave via SMI/MDIO instead of straps.

+----------+---------+-------+-------------------+----------------+------------------------+

| Register | Address | Bit   | Register Name     | Value to Write | Value Effect           |

+----------+---------+-------+-------------------+----------------+------------------------+

| RCSR     | 0x017   | bit 7 | RMII Clock Select | 1              | 50MHz Clock            |

| SOR2     | 0x468   | bit 4 | CFG_RMII_MODE     | 1              | RMII Interface         |

| SOR2     | 0x468   | bit 3 | CFG_XI_50_SLAVE   | 1              | Slave (External Clock) |

+----------+---------+-------+-------------------+----------------+------------------------+  

Thank you!

Hi Dan let me take a look at the table you sent over to me in email and respond after review. 

4. CEXT was tested and recommended for EMI/EMC testing. We did not see any major changes from an EMI/EMC standpoint from 2nF and 0.1uF CEXT so it should be ok. However per our validation and simulations we still do recommend the 2nF. 

3. It is not possible to access the PHY without a clock however, once its been provided you can access the SMI

Actually, SOR2 is read only.

To manually R/W register to RMII or MII mode you will configure bit 5 of reg 0x17. Currently the register is labeled as reserved which could be a datasheet typo.

Bit 5 outlines as 1 = RMII mode and 0 = MII mode which looks to be configuring as expected as well. This should allow you to read and write properly.

Bit 7 is selection for master or slave for RMII 

I'm on the last configuration strap.  Register BMCR (register address 0) bit 8 Duplex Mode.  Can I override the strap value via the SMI / MDIO ?  Is that was is meant for all bits marked with Type = "R/W,STRAP"?

Thanks for writing back. We've resigned ourselves to wedging some strap resistors into the PCB layout, particularly three, to set the MAC Mode and the PHY address as with your help it has become clear that those few strap resistors are unavoidable and must be included in the already packed PCB layout.

It's just an isolated question for the DP83826I. I want to make sure that when a SMI bit has "R/W,STRAP" in the "Type" column, that means I can overwrite the strap value via SMI.

In the specific case, the bit I am looking at is in register BMCR (register address 0), specifically bit 8 Duplex Mode.

• After the strap values latch, can I override this strap value via the SMI, that is, via MDC + MDIO?
• If you could confirm overriding the strap value via SMI is also possible for bits 12 (Auto-Negotiation Enable) and 13 (Speed Selection) in this same register BMCR (address 0) I would appreciate it as well.

The internal pull-down resistor would default this to "Auto Negotiation Disable" "Speed 10M" "Half-Duplex" mode, which is not what I want, so I would have to overwrite via SMI after the strap values latch. Please advise if I can override these strap values via the SMI.

Hi Dan,

Yes that is correct. You can override any strap configurations from hardware through SW R/W on registers. Especially ADDR 0x0000.