• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 35 subscribers
  • Views 471 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB941AS-Q1: Changing PLL

Brahim Salh
Intellectual 1345 points
Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: USB2ANY

Dear experts,

I'm using J721E EVM which has an integrated serializer UB941AS, I'm trying to run DSS examples through DSI output but I had an issue with pixel clock, it's always 75 MHz even I change it in the code.

Could you please tell how I can change PLL in this serializer? I couldn't find any register for this :(

Regards,

Brahim

  • 0
    TI__Guru**** 476245 points

    Hi Brahim,

    As we discussed last time, this question is not related to TDA4x. Can you please move it to SERDES forum?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Intellectual 1345 points

    Hi Hamzeh,

    Do you know which sequence of registers in UB941 to use to change pixel clock ?

    Regards,

    Brahim

  • 0 in reply to Brahim Salh
    TI__Guru** 103215 points

    Hello Brahim,

    It looks like from the board schematics that DS90UB941AS-Q1 is used in PCLK from external reference clock mode by default, however it may be easier to set the device up in PCLK from DSI clock mode assuming you do have control over the DSI clock source from the J7 and also you can configure the DSI clock as continuous. 

    To set up 941AS in PCLK from DSI clock mode, set register 0x56[1:0] = 00 and 0x4F[7] = 0. Also make sure that the J7 PCLK source is set to continuous mode. 

    If you still need to support external clock mode, then it looks like there are several stuffing options that need to be reworked on the board to connect the CDCL clock source. By the way I am referencing the design files here: www.ti.com/.../sprr411

    Best Regards,

    Casey

  • 0 in reply to Casey McCrea
    TI__Intellectual 1345 points

    Hi Casey,

    Thank you for your reply. That was exactly my registers configuration (0x56 = 00 and 0x4f = 04) but how can I select the value of pixel clock I want? I'm using USB2ANY to check the pixel clock value, it doesn't change even I change it in my application code, it always had the following values:

    0x56[1:0] = 00  ==> Pixel Clock = 75 MHz

    0x56[1:0] = 01  ==> Pixel Clock = 25 MHz

    0x56[1:0] = 10  ==> Pixel Clock = 25 MHz

    What sould I do for example to set Pixel Clock to 50 MHz?

    2) In which case I'm going to use to use M/N divider exist in 0x3A and 0x3B DSI offsets ? I tried to change the values of thses offsets by setting M to 1 and N to 4 (for 50 MHz) but they return to their default values (M=1, N=3) directly after the wrriting.

    Regards,

    Brahim

  • 0 in reply to Brahim Salh
    TI__Mastermind 25955 points

    Hi Brahim,

    Please disable DSI before trying to change these values, change the values, and then reenable DSI.  Please let me know if the issue persists after these steps.

    Sincerely,

    Bryan Kahler

  • 0 in reply to Bryan Kahler
    TI__Intellectual 1345 points

    Hi Bryan,

    I tried this step but it doesn't work, M and N dividers keep their default values. I set the register 0x01 to 08h value and then changed M and N using 3Ah and 3B offsets, finally I reenabled DSI by setting 0x01 register to 00h.

    I think this issue is also related to DSI configuration code made by Jacinto team, because in that code the pixel clock is set to 74.25 MHz and the application only work with this value.

    Regards,

    Brahim

  • 0 in reply to Brahim Salh
    TI__Mastermind 25955 points

    Hi Brahim,

    When writing to 0x3A and 0x3B, is 0x3A[7] and 0x3B[7] set high?

    Please try disabling DSI and set these registers with the enable bits selected before reenabling DSI.

    If this issue still occurs, please repeat, but set the device to force DSI CLK and disable reset of DSI on freq det change to see if the values changing are due to crossing the high/low thresholds.

    Sincerely,
    Bryan Kahler

  • 0 in reply to Bryan Kahler
    TI__Intellectual 1345 points

    Hi Bryan,

    It works, I forget to set 0x3A[7] to 1 so the M N values are not used. 0x3B[7] doesn't need to be high.

    For example, to write M=1 and N=4, I do:

    {0x16, 0x01, 0x08, 0x5},       //  Disable DSI

    {0x16, 0x40, 0x04, 0x5},
    {0x16, 0x41, 0x3A, 0x5},
    {0x16, 0x42, 0x81, 0x5},       //  set 0x3A[7] to 1 and write M=1

    {0x16, 0x40, 0x04, 0x5},
    {0x16, 0x41, 0x3B, 0x5},
    {0x16, 0x42, 0x04, 0x5},        //  Write N=4

    {0x16, 0x01, 0x00, 0x5},        //  Enable DSI

    0x16 is the address of UB941 and 0x5 is just a delay in ms.

    Thanks,

    Brahim